AM6442: eMMC pull-ups necessary or not?

The JEDEC eMMC standard defines internal pulls to be implemented in the eMMC device for data lines DAT1-DAT7. Immediately after entering the 4-bit mode, the device disconnects the internal pull-ups for DAT1-DAT3. Correspondingly, immediately after entering to the 8-bit mode the device disconnects the internal pull-ups for DAT1–DAT7.

The standard also defines host pull requirements for each signal except CLK, and says the host is expected to provide pull-ups to protect the CMD and DAT signals from floating when all device drivers are in a high-impedance state. Two pull-up types are defined for CMD, where R_OD is switched on and off by the host synchronously to open-drain and push-pull mode transitions. The other option is a fixed R_CMD pull-up when the host does not allow the switchable R_OD implementation.

The IO cells associated with AM64x MMC0_CMD, MMC0_DAT[7:0], and MMC0_DS pins have internal pulls which can be enabled via software. The MMC0 host controller does not dynamically control the internal pull-up/down for these IO’s. The internal pull-up will be turned on by default for MMC0_CMD and MMC0_DAT[7:0]. The internal pull-down will be turned on by default for MMC0_ DS. The internal pull-up/down functionality can be controlled via SW using the PHY Control 3 register inside the eMMC subsystem. MMC0_CLK does not have an internal pull-up/down since it is always driven. It is held low until SW driver writes to an MMR inside the controller to enable MMC0_CLK toggle.

The description above describes how the MMC0 pins operate once AM64x has been released from reset. However, we have implemented circuits that force all AM64x IOs into an off state until all power supplies are ramped to valid levels and reset is released. Therefore, the CMD, DAT0, DS, and CLK signals will not be pulled to a valid logic state by AM64x until it is released from reset.

We agree, external pull resistors should not be required for DAT1-DAT7 signals since the eMMC will have its internal pull-ups turned on until software tell the device to enter 4-bit or 8-bit mode. The eMMC standard does not mention a pull requirement for CLK because it expects the host to always drive this signal. Unfortunately, that will not be the case for AM64x while the system reset controller holds it in reset. Therefore, we recommend external pull-downs on CLK and DS, and external pull-ups on CMD and DAT0 to prevent the eMMC inputs from floating while AM64x is held in reset.

I will submit a request to update the schematic checklist to clarify external pull expectations for MMC0.

Regards,
Paul