omap3530 mcbsp1 transmission starts with end of my sdma copied buffer

There is a mistake in my description, the received buffer is in fact :

1) 0xC5 0xc6 ... 0xeb 0xec = last 40 bytes of transmitted buffer

2) 0x01 0x02...0x22 = first 34 bytes of transmitted buffer

3) 0x01 0x02...0x22 = first 34 bytes of transmitted buffer again

4) 0x23 ... 0xae : 140 bytes of transmitted buffer

0x804d3f40:  c5 c6 c7 c8 c9 ca cb cc cd ce cf d0 d1 d2 d3 d4  *................*
0x804d3f50:  d5 d6 d7 d8 d9 da db dc dd de df e0 e1 e2 e3 e4  *................*
0x804d3f60:  e5 e6 e7 e8 e9 ea eb ec 01 02 03 04 05 06 07 08  *................*
0x804d3f70:  09 0a 0b 0c 0d 0e 0f 10 11 12 13 14 15 16 17 18  *................*
0x804d3f80:  19 1a 1b 1c 1d 1e 1f 20 21 22 0f 10 11 12 13 14  *....... !"......*
0x804d3f90:  15 16 17 18 19 1a 1b 1c 1d 1e 1f 20 21 22 23 24  *........... !"#$*
0x804d3fa0:  25 26 27 28 29 2a 2b 2c 2d 2e 2f 30 31 32 33 34  *%&'()*+,-./01234*
0x804d3fb0:  35 36 37 38 39 3a 3b 3c 3d 3e 3f 40 41 42 43 44  *56789:;<=>?@ABCD*
0x804d3fc0:  45 46 47 48 49 4a 4b 4c 4d 4e 4f 50 51 52 53 54  *EFGHIJKLMNOPQRST*
0x804d3fd0:  55 56 57 58 59 5a 5b 5c 5d 5e 5f 60 61 62 63 64  *UVWXYZ[\]^_`abcd*
0x804d3fe0:  65 66 67 68 69 6a 6b 6c 6d 6e 6f 70 71 72 73 74  *efghijklmnopqrst*
0x804d3ff0:  75 76 77 78 79 7a 7b 7c 7d 7e 7f 80 81 82 83 84  *uvwxyz{|}~......*
0x804d4000:  85 86 87 88 89 8a 8b 8c 8d 8e 8f 90 91 92 93 94  *................*
0x804d4010:  95 96 97 98 99 9a 9b 9c 9d 9e 9f a0 a1 a2 a3 a4  *................*
0x804d4020:  a5 a6 a7 a8 a9 aa ab ac ad ae 00 00              *................*

Marc

Marc

I've used the DMA in some McBSP examples and not seen any strange behavior like you are reporting.

Can you provide me a dump of your DMA settings?

I've also attached some low level code that serves as a TX/RX McBSP example using DMA and multiple DMA buffers. It might be helpful to you.

  Paul

Hello Paul,

Thanks for your answer
It works fine with a 32 bits frame size, the issue is only with the 16 bits frame size.

According to  SPRUF98M – April 2010 – Revised December 2010 §21.4.2 :
"The McBSP registers (DRR_REG and DXR_REG) are limited to 32-bit data
accesses (L4 Interconnect). 16-bit and 8-bit is not allowed and can corrupt
register content."

However, according to the very same document §21.6.1 :
"The McBSP data registers (that is, DXR_REG for data transmit and DRR_REG
for data receive) support 8/16/32-bit data accesses. "

Do you know which one is correct ?

Marc

Paul,

I did 2 tests, one with ES=32 bits and one with ES=16 bits.
I turn off and on my target before each test.

First, my 32 bits DMA settings that works :
-> vxbOmap35xxMcBsppDmaShow
DMA4_REVISION=0x00000040
OMAP_DMA_SYSSTATUS=0x00000001
OMAP_DMA_OCP_SYSCONFIG=0x00000000
OMAP_DMA_CAPS_0=0x000c0000 OMAP_DMA_CAPS_2=0x000001ff OMAP_DMA_CAPS_3=0x000000f3 OMAP_DMA_CAPS_4=0x000000fe
OMAP_DMA_GCR=0x00010080 (fifos)
OMAP_DMA_CCR(0)=0x0004101f (channel ctrl)
OMAP_DMA_CLNK_CTRL(0)=0x0000000b (channel link)
OMAP_DMA_CICR(0)=0x00000020 (interrupt ctrl)
OMAP_DMA_CSR(0)=0x00000000 (channel status)
OMAP_DMA_CSDP(0)=0x003f0376 (src/dst params)
OMAP_DMA_CEN(0)=0x00000076 (nbelem in a frame)
OMAP_DMA_CFN(0)=0x00000001 (nbframe in block)
OMAP_DMA_CSSA(0)=0x804d5c00 OMAP_DMA_CDSA(0)=0x48074008 (src/dst start address)
OMAP_DMA_CSEI(0)=0x00000000 OMAP_DMA_CSFI(0)=0x00000000 (src index)
OMAP_DMA_CDEI(0)=0x00000000 OMAP_DMA_CDFI(0)=0x00000000 (elem/frame dst index)
OMAP_DMA_CSAC(0)=0x804d5dd8 OMAP_DMA_CDAC(0)=0x48074008 (src/dst current address)
OMAP_DMA_CCEN(0)=0x00000076 OMAP_DMA_CCFN(0)=0x00000000 (current elem/frame number)
OMAP_DMA_COLOR(0)=0x00e1fdf7

Of course, since I use 32 bits ES to write 16 bits frames, half of my buffer is never transmitted,
this explains 02 01 followed by 06 05 and the lost 04 03 in my received buffer.
In order to receive the same number of bytes I send 472 bytes instead of 236 :

-> d 0x804d4c00,236,1
0x804d4c00:  02 01 06 05 0a 09 0e 0d 12 11 16 15 1a 19 1e 1d  *................*
0x804d4c10:  22 21 26 25 2a 29 2e 2d 32 31 36 35 3a 39 3e 3d  *"!&%*).-2165:9>=*
0x804d4c20:  42 41 46 45 4a 49 4e 4d 52 51 56 55 5a 59 5e 5d  *BAFEJINMRQVUZY^]*
0x804d4c30:  62 61 66 65 6a 69 6e 6d 72 71 76 75 7a 79 7e 7d  *bafejinmrqvuzy~}*
0x804d4c40:  82 81 86 85 8a 89 8e 8d 92 91 96 95 9a 99 9e 9d  *................*
0x804d4c50:  a2 a1 a6 a5 aa a9 ae ad b2 b1 b6 b5 ba b9 be bd  *................*
0x804d4c60:  c2 c1 c6 c5 ca c9 ce cd d2 d1 d6 d5 da d9 de dd  *................*
0x804d4c70:  e2 e1 e6 e5 ea e9 ee ed f2 f1 f6 f5 fa f9 fe fd  *................*
0x804d4c80:  02 01 06 05 0a 09 0e 0d 12 11 16 15 1a 19 1e 1d  *................*
0x804d4c90:  22 21 26 25 2a 29 2e 2d 32 31 36 35 3a 39 3e 3d  *"!&%*).-2165:9>=*
0x804d4ca0:  42 41 46 45 4a 49 4e 4d 52 51 56 55 5a 59 5e 5d  *BAFEJINMRQVUZY^]*
0x804d4cb0:  62 61 66 65 6a 69 6e 6d 72 71 76 75 7a 79 7e 7d  *bafejinmrqvuzy~}*
0x804d4cc0:  82 81 86 85 8a 89 8e 8d 92 91 96 95 9a 99 9e 9d  *................*
0x804d4cd0:  a2 a1 a6 a5 aa a9 ae ad b2 b1 b6 b5 ba b9 be bd  *................*
0x804d4ce0:  c2 c1 c6 c5 ca c9 ce cd d2 d1 d6 d5              *................*

Then my 16 bits DMA settings that fails, I only modify ES to 16 bits :

-> vxbOmap35xxMcBsppDmaShow
DMA4_REVISION=0x00000040
OMAP_DMA_SYSSTATUS=0x00000001
OMAP_DMA_OCP_SYSCONFIG=0x00000000
OMAP_DMA_CAPS_0=0x000c0000 OMAP_DMA_CAPS_2=0x000001ff OMAP_DMA_CAPS_3=0x000000f3 OMAP_DMA_CAPS_4=0x000000fe
OMAP_DMA_GCR=0x00010080 (fifos)
OMAP_DMA_CCR(0)=0x0004101f (channel ctrl)
OMAP_DMA_CLNK_CTRL(0)=0x0000000b (channel link)
OMAP_DMA_CICR(0)=0x00000020 (interrupt ctrl)
OMAP_DMA_CSR(0)=0x00000000 (channel status)
OMAP_DMA_CSDP(0)=0x003f0375 (src/dst params)
OMAP_DMA_CEN(0)=0x00000076 (nbelem in a frame)
OMAP_DMA_CFN(0)=0x00000001 (nbframe in block)
OMAP_DMA_CSSA(0)=0x804d5c00 OMAP_DMA_CDSA(0)=0x48074008 (src/dst start address)
OMAP_DMA_CSEI(0)=0x00000000 OMAP_DMA_CSFI(0)=0x00000000 (src index)
OMAP_DMA_CDEI(0)=0x00000000 OMAP_DMA_CDFI(0)=0x00000000 (elem/frame dst index)
OMAP_DMA_CSAC(0)=0x804d5cec OMAP_DMA_CDAC(0)=0x48074008 (src/dst current address)
OMAP_DMA_CCEN(0)=0x00000076 OMAP_DMA_CCFN(0)=0x00000000 (current elem/frame number)
OMAP_DMA_COLOR(0)=0x00f1fff7

I send a 236 bytes buffer and I receive random bytes :
-> d 0x804d4c00,236,1
NOTE: memory values are displayed in hexadecimal.
0x804d4c00:  27 05 0b b2 dd 8c ee 87 ea b1 2d d3 0b c3 75 65  *'.........-...ue*
0x804d4c10:  1f c6 40 80 12 4d 69 f7 96 45 f2 9e c6 47 aa 9b  *..@..Mi..E...G..*
0x804d4c20:  c3 fa c9 aa 99 b2 2b 17 d5 bb d6 4a cd aa 8a de  *......+....J....*
0x804d4c30:  9f 4c 1c 8e df 93 f2 30 a6 88 c0 2f df 8d f3 d4  *.L.....0.../....*
0x804d4c40:  22 98 45 57 d6 7f 05 cb 73 d0 c7 b9 32 a1 db 83  *".EW....s...2...*
0x804d4c50:  00 f9 ee 2c 1d bf ad 47 19 51 98 4e 20 45 0b 6b  *...,...G.Q.N E.k*
0x804d4c60:  59 c1 ef 2b af fa e7 87 4f 43 cf c3 a4 d6 b0 3d  *Y..+....OC.....=*
0x804d4c70:  b3 49 3e 46 87 6d 38 8f e6 e7 e7 e6 9e 86 17 e6  *.I>F.m8.........*
0x804d4c80:  c2 46 9d 48 c3 75 3b c0 68 b8 94 3a 74 72 72 8e  *.F.H.u;.h..:trr.*
0x804d4c90:  29 48 98 76 a9 bf b0 63 ff b3 2e 0d 36 5d 62 b2  *)H.v...c....6]b.*
0x804d4ca0:  b3 fa 24 5a c5 9e 6e 0e be 2e e1 ed 27 cb 0d 1c  *..$Z..n.....'...*
0x804d4cb0:  5f 9b 88 51 98 6a 55 9e b9 82 20 9c d5 d6 a3 fe  *_..Q.jU... .....*
0x804d4cc0:  bf a2 03 5a e8 04 64 70 24 80 f1 ac 26 dc 2e ec  *...Z..dp$...&...*
0x804d4cd0:  b4 17 a8 5c 21 b0 f9 47 05 38 a0 f3 83 05 87 4e  *...\!..G.8.....N*
0x804d4ce0:  bc 55 10 a6 14 b5 e6 ae 31 ae f3 1b              *.U......1.......*

Marc

Marc

marc seninge said:

Hello Paul,

Thanks for your answer
It works fine with a 32 bits frame size, the issue is only with the 16 bits frame size.

According to  SPRUF98M – April 2010 – Revised December 2010 §21.4.2 :
"The McBSP registers (DRR_REG and DXR_REG) are limited to 32-bit data
accesses (L4 Interconnect). 16-bit and 8-bit is not allowed and can corrupt
register content."

However, according to the very same document §21.6.1 :
"The McBSP data registers (that is, DXR_REG for data transmit and DRR_REG
for data receive) support 8/16/32-bit data accesses. "

Do you know which one is correct ?

Marc

That is a documentation issue. Tests I have done in the past show that it is necessary to use 32-bit accesses. 8-bit and 16-bit should not be used.

If you use 32-bit accesses is you issue solved?

  Paul

Hello Paul,

Many thanks for your answer.

Yes, according to tests I did, I guess it works with 32-bit access but it doesn't work with 16 bits access.

However, I am confused by Brad Griffis answer to the post :

"McBSP I2S Configuration"

"

8-, 16-, and 32-bit accesses are allowed for DXR and DRR.  All other McBSP registers only support 32-bit accesses.  So changing the DMA address should be fine.  I expect that will solve your issue though please confirm.

Best regards,
Brad"

Marc

Marc

Yes, I think this is also an error.  I know for sure that 16-bit and 8-bit writes may lead to incorrect data being transmitted.

  Paul