DRA821U: Coherent access from R5F to data handled by A72SS

Dear Kishi, 

With respect to cache coherency, R5F and A72 are different. A72 make its cache visible to our coherent shared memory controller (MSMC). Meaning, A72 L2 cache content can be snooped. But R5F doesn't support AMBA protocol, its cache cannot be snooped. To "see" what is in R5F cache, one has to flush R5F cache to the main memory.

Now, when we talk about data sharing, we often use producer and consumer model. Let's use R5F and A72 example:

1. If A72 is the producer, R5F is the consumer. When R5F reads the shared location which is updated by A72, MSMC would be able to snoop A72 and provide the latest data from A72 cache to R5F. This is because A72 support full cache coherency;

2. If R5F is the producer, A72 is the consumer, the case is different. Because R5F doesn't support cache snoop by external coherent request, SW has make sure SW data coherency is executed. Meaning, a cache writeback and invalidate should be done on R5F cache before informing the consumers (including A72) the data is available to share. Now, when A72 reads the shared location which is updated by R5F, the updated data is expected to be in main memory.

So, looks like you are asking my case #1 support. Therefore, except by setting the shared memory space in A72 page tables as desired, you don't need to do neither methods in your suggestions. The TDA4x device takes care your case naturally. 

Thanks,

Kai