TDA4VM: how to configure the clock(HFOSC1) for MAIN domain correctly？

Hi,

Which bootloader are you using? SPL/u-boot or SBL?

Regards,
Stanley

the bootloader is uboot spl

Hi,

Could you please look at this response: https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1010918/tda4vm-how-to-enable-hfosc1/3746912#3746912?

- Keerthy

hi keerth,

thanks for your reply.

Address 0x4300_8014 mentioned the links has not found in TRM. and the register CTRLMMR_WKUP_LFXOSC_CTRL is used to enable WKUP_LFOSC0 oscillator, HFOSC1 is not described in TRM.

however, the requirements is that how to configure external oscillator(HFOSC1) for MAIN domain, the related register are as follows, and when we try to configure it, the system crashes.

thanks

xiaowei

hi Kevin,

thanks for your reply.

Is it means that if the HFOSC1_CTRL register is written from 0x80 to 0x00, then external oscillator(HFOSC1) can be chosen as PLL reference clock of MAIN domain, and no other register need to be configured (including CTRLMMR_WKUP_MAIN_PLLn_CLKSEL as metioned above)?

By the way, which state is recommended for HFOSC1_CTRL configuration? boot, runtime...?

thanks

xiaowei

Xiaowei,

Writing HFOSC1_CTRL from 0x80 to 0x00 turns HFOSC1 ON.

If you want to use it for a specific PLL, you will still need to select it as the source of that PLL (e.g. _CLKSEL).

HFOSC1 is a secondary clock source; you should use it as needed.  I do not understand the last question.

Kevin

hi kevin,

thanks for your reply.

the background of last quesetion is “when we selects clock(HFOSC1) as PLL reference clock (by configuring CTRLMMR_WKUP_MAIN_PLLn_CLKSEL) before boot of MAIN domain, the system crash and not work. (the HFOSC1 is not turn ON because of lack of above info)”.  And we guess that the configuration may be at the wrong state.

So is there a recommended system state for PLL configuration?

xiaowei.duan

Xiaowei,

A couple of questions:

-1- what code are you running? Linux / RTOS / QNX???  Most of these platforms would have configured the PLLs in some way.

-2- what are the frequencies of HFOSC0 and HFOSC1?

-3- at what point in the code are you trying to change to HFOSC1? Have the PLLs been initialized and started clocking circuitry?

-4- what core are you using to change the source of the oscillator?

Kevin

hi Kevin,

1. A72 runs QNX, MCU_R5 runs AutoSAR

2. Both frequencies of HFOSC0 and HFOSC1 are 19.2MHz

3. We're trying to change the clock in MCU_R5 Bootloader, at which time the PLLs have been initialized and started the clocking.

4. Change following register CLK_SEL from 0 to 1

BR

xiaowei.duan

Hi Kevin,

Thanks for your reply, and we will try to verify the recommended configuration.

BR

xiaowei.duan

Xiaowei,

What is the reason you are using 19.2MHz on both OSC0 and OSC1? Why are you not driving the PLLs with OSC0?

Kevin

hi Kevin,

OSC1 is considered as reference clock because of the requirement about Freedom From Interference between MAIN domain(ASIL B) and MCU domain(ASIL D).And the following description is mentioned in safety manual.

BR

xiaowei.duan

xiaowei duan said:

Thanks for your reply, and we will try to verify the recommended configuration.

Hi xiaowei.duan,

I believe this is still pending from your side. Let us know once you are done."

- Keerthy