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TDA4VM: LPDDR4 simulation setting

Jiacai Wang
Intellectual 420 points
Part Number: TDA4VM

Hi TI Team,

I do not how to choose following parameters when I simulate

MT53D1024M32D4 LPDDR4;

I known MT53D1024M32D4 involved quad dies, 2 channels and 2 ranks

. 

Array configuration: 1024 Meg × 32 (2 channels ×16 I/O) 1024M32;

Device configuration: 512M16 × 4 die in package D4

Please help me to confirm MT53D1024M32D4 is 2 DIMM slots and 2 ranks, or 1 slot and 4 ranks ?

Select the number of DIMM slots and the number of DRAM ranks per slot.  For on-board memory designs (no DIMMs), either set the number of slots to zero and then set the total number of DRAM ranks, or treat the on-board memory as residing within virtual slots.  For designs with a mix of on-board memory and DIMMs, consider the on-board memory as a slot.  After setting the slot and rank configuration, associate the DRAM devices listed on the left to specific ranks of memory on the right.  Slots and ranks allocated are not required to actually be populated.

Thanks,

Joseph

  • +1
    TI__Mastermind 34690 points

    Hi,

    I am not sure how the tool you have referenced uses these parameters, but per the instructions, it sounds like you can set DIMMs to 0 (as this should be an "on-board memory design"). I will forward this to our EVM design team to see if they have any additional comment. You might also consider reaching out to the company who created this tool to clarify the purpose of those parameters.

    Thanks,
    Kevin

  • +1 in reply to Kevin S
    TI__Mastermind 47580 points

    This is really a tool-specific question, and should be sent to the tool manufacturer for clarification.  Customer appears to correctly interpret the memory architecture (quad die, 2 channels with 2 ranks).