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AM6442: DMSS / UDMA with external trigger/synchronisation?

fmdhr
Expert 1550 points

Part Number: AM6442
Other Parts Discussed in Thread: AM3359

Hi,

we plan to modernize our SoM based on the AM3359 and check the AM6442 as option.

In one of our applications we used the EDMA for communication with a CLPD/FPGA via GPMC. The EDMA is (repeatedly) triggered by a GPIO signal, and using EDMA linking and chaining we built a communication nearly completely without CPU interaction (interrupt). Chained EDMA reads and writes the CPLD and clears the GPIO and EDMA event flags with a 10 us (100kHz) rate, the next GPIO event starts a next (linked) EDMA transfer etc., CPU is involved e.g. every 500 us for 50 cycles.

The TI application report "Migrating Applications from EDMA to UDMA using TIRTOS" (Aug 1st 2018) says (Table 1 p. 10), that a "Synchronisation based on Event from peripheral" is no longer available with AM64xx DMSS / UDMA or how it is named. As far as I can see, only CPU, UDMA itself and PSI-L can trigger UDMA transfers.

Is there a way to realise our application or do we have to use other hardware?

Thanks & regards,

Frank

  • 0
    TI__Mastermind 27355 points

    Hi Frank,

    I will need some time to look into this - I will follow up by Friday with a reply. 

    Regards,
    Sahin

  • 0
    TI__Mastermind 27355 points

    Hi Frank,

    I am sorry for the delay. I will need some more time for this - I will follow up early next week.

    Regards,
    Sahin

  • 0 in reply to Sahin Okur
    Expert 1550 points

    Hi Salin,

    any news meanwhile?

    Thanks,

    Frank

  • 0 in reply to fmdhr
    TI__Mastermind 27355 points

    Hi Frank,

    Yes, just got confirmation from the SOC architect that yes, you can use a GPIO to trigger the UDMA via the DMSS L2G block. The DMSS L2G allows for interrupt inputs from GPIO as shown below: 

    Regards,
    Sahin

  • 0 in reply to Sahin Okur
    Expert 1550 points

    Hi Sahin,

    thank you for the information. Following your hint, yesterday I spent several hours to find out which registers to program to trigger the DMSS by GPIO m.n to move some bytes from address x to address y. I found it hard to understand the whole system reading only the TRM. The subsystems are descibed in detail, but isolated from each other. There is no general overview, there are only a few figures that describe interdependencies. A lot of abbreviations are used but not explained when they appear. E.g. 11.2.1.2.5 DMSS L2G Interrupt Inputs p.2983 in your reply: many pages later, on page 3244 in Table 11-523. intaggr_l2g, one may guess that it means "local to global". Other examples are IA, SA in Figure 11-1. PKTDMA Block Diagram, KS3, MMRs, SAUL0, CBASS0, ..., some of them are never explained in the TRM. (TRM is the Technical Reference Manual SPRUIM2B).

    The DMSS may be a great improvement compared to the EDMA3, but the description in the manual IMHO is not. Is there some other literature to get a better introduction?

    Regards,

    Frank

    PS: Sorry for the typo in your name in my previous message.

  • 0 in reply to fmdhr
    TI__Mastermind 27355 points

    Hi Frank,

    Thank you for bringing this up. We're currently working on providing more concrete guidance on this topic soon. I will follow up with a reply here. 

    Regards,
    Sahin

  • 0 in reply to Sahin Okur
    TI__Mastermind 27743 points

    Hi Frank,

    Sorry for delay in response here. Please let us know if you still need help.

    Regards,

    Prasad

  • 0 in reply to Prasad Jondhale
    Expert 1550 points

    Hi Sahin & Prasad,

    thank you for your replies. I meanwhile have the DMSS/UDMA running together with the GPMC (modified example from the MCU+), and I tried the GPIO interrupt example. Next steps would be to generate an event for the DMASS from the GPIO, trigger the DMA to the GPMC and then reset/acknowledge the GPIO event using a (chained) DMA transfer.

    It would be nice if you have some hints, e.g. which driver api functions can be used for that etc.

    Thanks & regards,

    Frank

  • 0 in reply to fmdhr
    TI__Mastermind 27355 points

    Hi Frank,

    Please see the attached example project for reference code. This example triggers the DMA from an IEP event, but more importantly shows how to setup the interrupt router to trigger the DMA via the DMSS L2G block. You will need to follow the same path to trigger the DMA with a GPIO. 

    udma_iep_cmp_trigger_am64x-evm_r5fss0-0_nortos_ti-arm-clang.zipAM64x AM243x UDMA IEP EPWM Software Example.pptx

    I hope this helps. Please let us know if you have any questions.

    Regards,
    Sahin

  • 0 in reply to Sahin Okur
    Expert 1550 points

    Hi Sahin,

    thank you for the example project. I got it compiled, but I had a problem to get it run on the AM64EVM: the accesses to the ICSS IEP (configure_iep() etc.) ended up in the HwiP_data_abort_handler(). There seems to be no driver / initialisation for the ICSS in the project. A

        /* we must switch on the icss clock before we can access registers */
        SOC_moduleClockEnable(TISCI_DEV_PRU_ICSSG1, 1);

    solved the problem, may be you want to fix this.

    I now have to go step by step through the details, and the example code surely will help.

    Thanks & regards,

    Frank