DRA750: DRA750 MMC2-eMMC interface

Ray Vincent Aranzaso

Part Number: DRA750

Hi,

Good Day. I have a customer who has a query about DRA750 MMC2-eMMC interface. Please see below for hi query. Thank you very much.

DRA750 data sheet chapter 7.24.2, describes available emmc bus speeds. One of them is HS200, 8 bit, half cycle.
Its strange because emmc Jedec standard doesn’t supports HS200 half cycle (its supposed to be just HS200).
Can you please explain what the meaning of this half cycle?

Best Regards,

Ray Vincent

over 5 years ago

0 Shiou Mei Huang over 5 years ago

TI__Genius 10180 points

Ray,

The MMC module was designed to launch data on the falling edge, thus the half cycle timing presented in Switching Characteristics for MMC2 - JEDS84 HS200 Mode.

Thanks & Regards,

Shiou Mei

0 Ray Vincent Aranzaso over 5 years ago in reply to Shiou Mei Huang

TI__Mastermind 18180 points

Hi Shiou,

Good Day. Please se below the response of our customer to your reply. Thank you very much.

Sorry just to clarify, TI HS200 half cycle H200 mode is normal EMMC H200 mode. Am I correct? None of emmc data sheet (Micron or another) declares HS200 half cycle modes only HS200 mode.

Best Regards,

Ray Vincent

0 Shiou Mei Huang over 5 years ago in reply to Ray Vincent Aranzaso

TI__Genius 10180 points

Ray Vincent,

JEDEC industrial standard defines the HS200 output mode with data launching off of the rising edge. TI DRA75x MMC modules launch data off of the falling edge, thus why it was called out to be half cycle. Aside for this difference, the HS200 mode is compliant to JEDEC timing limits, and can be interfaced like normal.

Best Regards,

Shiou Mei

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DRA750: DRA750 MMC2-eMMC interface