Other Parts Discussed in Thread: OMAP3530, SYSBIOS
Hi,
I'm trying to get GPIO Interrupts working on the C64P processor on the Omap3530 using SYS/BIOS.
I'm obviously missing some configuration step (or two) but can't figure out what I'm missing.
I am running the DSP code under CCSv4 and using DSP/Bios v6.x. The code is a modified form of
the "Clock" template
Background:
My hardware setup is that I'm triggering an ADC via GPIO 133 and getting a "Done" response back on pin GPIO 139 (falling edge). My goal is to trigger an HWI thread on the
interrupt.
Trigger Output: GPIO_133
Done Output: GPIO_139 (GPIO Bank 5, bit 0x800)
GPIO Setup:
The GPIO is set up correctly to see the input and outputs. The input is configured for a falling edge interrupt in and is correctly getting the event in the irqstatus2 register.
#define GPIO_139 0x800
GPIO_Bank5->setirqenable2 = GPIO_139;
GPIO_Bank5->fallingdetect = GPIO_139;
// from the TRM: the global event ID for GPIO bank 5 is 77, IVA2_IRQ[32]
HWI Setup:
In main I am setting up the HWI like so (pseudo code):
// C64+ processor specific version of HWI (for EventMap call)
#include <ti/sysbios/family/c64p/Hwi.h>
.. in main()
UInt gpio_event = 77; // interrupt event
UInt gpio_irq = 5;
Error_Block eb;
Hwi_Params hwiParams;
.... GPIO and timer setup stuff ....
// Create a hardware interrupt source
Hwi_Params_init(&hwiParams);
hwiParams.arg = 5;
hwiParams.enableInt = FALSE; // start later..
// connects the CPU event to a specific interrupt channel
// this is specific to the C64+ HWI implementation
Hwi_eventMap(gpio_irq, gpio_event);
// Create the hardware interrupt source
Hwi_create(gpio_irq, hwiFunc, &hwiParams, &eb);
// enable the hardware ISR (GIE) and IEC
Hwi_enableInterrupt(gpio_irq);
... clock and BIOS_Start....
Testing:
To test the code I am using a timer thread which pulses GPIO_133, and produces a done falling edge on GPIO_139 (verified). As I said, I can see the proper bit is
set in the GPIO bank 5 irqstatus2 register. But the attached HWI routine (hwiFunc) never runs.
In the Core registers:
CSR: GIE bit is enabled
on the call:
Hwi_enableInterrupt(gpio_irq);
IER: gets 0x20 set (IRQ5)
In the IC registers:
Looking at INTMUX1 I get 0x07064d04 which correctly shows event 7 mux'd to IRQ5 but don't see anything coming in on IC->EventFlag2 which should see 0x2000 for event 77. I then attempted to force an interrupt by writing to EventSet2, which causes the EventFlag to latch but does not trigger the HWI thread either.. If I force the event via write to EventFlag2 I would hope I would
Questions:
Did I miss anything in the above configuration?
With all these levels of processing, i.e. GPIO-> IVA2 IC -> C64X+ -> Sys/BIOS what is the best way
to verify/test the irq configuration. Is there a way to force an interrupt at the various
levels to work "backwards" down the stack?
-Thanks,
Bill