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DM6467T PCI interrupt example

Isara
Intellectual 1130 points

I have a question from customer asking for example code for DM6467T PCI controller ( From our WiKi link below, a suggestion on PCIU interrupt workaround ) Is there an example of a modified device driver and a sketch of the PCI and GPIO wiring needed to implement this available?   

 

http://processors.wiki.ti.com/index.php/DaVinci_PSP_03.02_Linux_Installation_User_Guide

  • DM6467/T PCI Host on default EVMs cannot receive PCI interrupts from targets connected over the bus (INTA to INTD).

Workaround: Connect INTA-D lines from PCI targets directly to available GPIO interrupt pins on DM6467/T PCI Host and add interrupt hooking code in DM6467/T PCI Host controller driver as applicable. In this case, ensure that GPIO bank 0 interrupt, pin direction (in) and trigger (rising edge), pin muxing (e.g., disable AUDCLK0 if using GPIO3) is configured in board specific file before any PCI target driver supposed to use GPIO interrupts is loaded.

Regards,

Isara

  • 0
    TI__Expert 5685 points

    Isara,

    I am creating an appnote on wiki describing the setup. Let me know if it answers your query.

    The link is: http://processors.wiki.ti.com/index.php/DM6467_PCI_Host_Interrupts

       Hemant

  • 0
    TI__Intellectual 1130 points

    Hi Hermant,

     

    I've got another question from customer about PCI Host support on the DM6467T.

     

    We've got the DM6467T EVM sitting in a PC motherboard.  It boots over PCI using the bootstrap scheme described by TI (by the way, shall I send you the changes needed for dm646x_pci_targetdrv.c to build on 64-bit Linux?  It's rather annoying that TI did not write the driver properly to support 64-bit, which is most systems these days; it is disheartening when TI support tools do not even compile).  The EVM system then comes up normally; I hacked arch/arm/mach-davinci/pci-dm646x.c to always act as a bus master, otherwise it just comes up as a PCI slave and does not enumerate.

     

    So far so good---in /proc/bus/pci/devices I can see several motherboard resources and read their configuration registers, so it is participating in the motherboard's PCI segment.

     

    What I don't see, however, are the bridges to the other PCI buses in the system, such as the bridge to the PCI segment containing the motherboard's USB controllers, or the Intel bridge to the VGA devices or to main memory.