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TMS320C6678: cache writeback failure

Zhong Qu
Prodigy 70 points

Part Number: TMS320C6678

Execute cache_inv, but the data in the cpu cache is not written back, and the data in the memory has not changed

  • 0
    TI__Mastermind 25535 points

    Dear Customer,

    Good day.

    To have a closer look on this issue, please provide details like the name of the Software package used. Is it your own code or the TI provided..

    The function, cache_inv is part of which Software and how do you execute it etc... 

    Regards

    Shankari

  • 0 in reply to Shankari G
    Prodigy 70 points

    Using the csl library package in mscdk2.1.2, the short-range writeback is operable, but the large-range writeback has no effect. I used a program written by myself.

  • +1 in reply to Zhong Qu
    TI__Mastermind 25535 points

    Dear Customer,

    Good day!

    When I looked into the reference of CSL function, given below, make sure the "blockPtr" are aligned on the cache line size......

    For more info on how to align, please look at the function, CacheP_wbInv() which in turn uses this function. You can find it in CacheP_nonos.c under C:\ti\pdk_c665x_2_0_16\packages\ti\osal\arch\core\c6x

    (In addition to that, Please have a look at the release notes of CSL for Known bugs....)

                  Zhong says " the short-range writeback is operable, but the large-range writeback has no effect. "

    Please elaborate, what is short range and large range? Do you mean the size of the bytes ? If yes, please, specify.

    ----

    DOxygen files-- html 

    csl_cacheAux.h File Reference 

    file:///C:/ti/pdk_c665x_2_0_16/packages/ti/csl/docs/doxygen/html/csl__cache_aux_8h.html

    CACHE Functions

    file:///C:/ti/pdk_c665x_2_0_16/packages/ti/csl/docs/doxygen/html/group___c_s_l___c_a_c_h_e___f_u_n_c_t_i_o_n.html#ga54aa28abf1e8cb611e48dedbc951a87b

    -----

    CACHE_wbInvL2

    Description
    This function is used to write back and invalidate the contents of the L2 Cache. Although the block size can be specified in the number of bytes, the cache controller operates on whole cache lines. To prevent unintended behavior "blockPtr" should be aligned on the cache line size and "byteCnt" should be a multiple of the cache line size.

    Arguments

           blockPtr      Address of the block which is to be written back & invalidated
       byteCnt       Size of the block to be written back & invalidated.
       wait          Indicates if the call should block or not.

    Return Value
    None

    Pre Condition
    None

    Post Condition
    The contents of the L2 Cache are being written back & invalidated.

    Writes
    CGEM_L2WIBAR_ADDR,CGEM_L2WIWC_WC

    Example

         Uint8* ptr_buffer;

     // Invalidate the contents of the buffer.
     CACHE_wbInvL2(ptr_buffer, 100, CACHE_WAIT);
    ==============================


    Regards
    Shankari