Part Number: DRA821U
Other Parts Discussed in Thread: DRA821
From U-boot file ./board/ti/j721e/README, it is understood bootrom will load SPL, where SPL will load sysfw.itb then do DDR configuration.
As DDR configuration is done as part of SPL code, where SPL code will be running, is it on SRAM?
DRA821 is having three SRAM's
1. MCU Domain --> 1MB SRAM
2. Main Domain --> 512MB SRAM
Multicore shared memory controller - -> 1MB(With ECC)
