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AM6442: GPMC, 32-bit non-muxed data/address mode

Steven Hansen
Intellectual 696 points

Part Number: AM6442

Hi TI team,

We have an ASIC with a 32-bit SRAM interface that uses separate data and address lines (32 data lines, 9 address lines). We'd like to use AM6442's GPMC to communicate with the ASIC, but I notice the TRM for AM6442 does not indicate support for "non-multiplexed 32-bit address/data". However, the device seems to have the correct pins to support this mode, and I also found an E2E post that says this mode is supported:

https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1004809/am6442-about-general-purpose-memory-controller-gpmc/3717960

Can you clarify if 32-bit non-multiplexed mode is supported? If so, will the TRM be updated to reflect this mode?

  • +1
    TI__Mastermind 30601 points

    Hi Steven,

    AM644x GPMC supports supports "non-multiplexed Address Data 32-Bit Device". The address bus is the same as "non-multiplexed Address Data 16-Bit Device", except both A1 and A0 are not used. The GPMC0_AD[31:0] bus contains the 32-bit data.

    I will file a bug to update the TRM Table 12-3390. GPMC Pin Multiplexing Options and to add a corresponding figure for GPMC to 32-Bit Non-Multiplexed Memory.

    We cannot add every mode, but this is a good one to document clearly.

    Thanks for the feedback.

    Regards,
    Mark