Hi TI support team,
Our TDA4 is on a custom board and the current SDK version is 7.2.
When I set the clock frequency to 100K in the MCU_I2C0 device tree, the oscilloscope shows the frequency of MUC_I2C0_SCL is 554.3K.
It does not meet my expectations.
However, The clock frequency works fine in SDK 6.2.
The following code is the partial code in function omap_i2c_init(struct omap_i2c_dev *omap) in i2c-omap.c
if (!(omap->flags & OMAP_I2C_FLAG_SIMPLE_CLOCK)) {
/*
* HSI2C controller internal clk rate should be 19.2 Mhz for
* HS and for all modes on 2430. On 34xx we can use lower rate
* to get longer filter period for better noise suppression.
* The filter is iclk (fclk for HS) period.
*/
if (omap->speed > 400 ||
omap->flags & OMAP_I2C_FLAG_FORCE_19200_INT_CLK)
internal_clk = 19200;
else if (omap->speed > 100)
internal_clk = 9600;
else
internal_clk = 4000;
fclk = clk_get(omap->dev, "fck");
if (IS_ERR(fclk)) {
error = PTR_ERR(fclk);
dev_err(omap->dev, "could not get fck: %i\n", error);
return error;
}
fclk_rate = clk_get_rate(fclk) / 1000;
clk_put(fclk);
/* Compute prescaler divisor */
psc = fclk_rate / internal_clk;
psc = psc - 1;
I think the SYS_CLK frequency is wrong.
On the line 23, fclk_rate = clk_get_rate(fclk) / 1000;
I found clk_get_rate(fclk) returns 16,000,000 instead of 96,000,000, which makes the caculation of psc incorrect.
psc = fclk_rate / internal_clk - 1 = 16000 / 4000 -1 = 3
The following table is the I2C register value table.
The following code is the device tree we set for MCU_I2C0.
&mcu_i2c0 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&mcu_i2c0_pmic_pins_default>;
clock-frequency = <100000>;
};
mcu_i2c0: i2c@40b00000 {
compatible = "ti,j721e-i2c", "ti,omap4-i2c";
reg = <0x0 0x40b00000 0x0 0x100>;
interrupts = <GIC_SPI 852 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
clock-names = "fck";
clocks = <&k3_clks 194 0>;
power-domains = <&k3_pds 194 TI_SCI_PD_EXCLUSIVE>;
};
BTW, We also checked the SOC_I2C.
Its frequency is correct.
Best regards,
Elsun Liu
