Hello Team,
When using TSR to convey clock information across cores (e.g. as is done for CPTS time in the PDK in main_tirtos.c, "CpswRemoteApp_initSyncTimer" ),
I understand that the frequency of the callbacks depends on the PWM settings of the clock used to trigger the HW push events (e.g. GTC in the example).
Is there a limit to how fast these callbacks can be processed, other than the limits of the PWM settings? Could I for example receive callbacks at a frequency of 1ms?
The reason for my question is: I am trying to determine how quickly all cores can get access to PTP time (i.e. CPTS time of CPSW9G) in theory.
I did see in the TRM that HW push events are expected to be low-frequency, as the FIFO storing them is quite small. But I think that should be ok for my use case. I am thinking the fastest way for remote cores to get access to CPTS time would be:
- on startup, setup TSR callback to be very fast (e.g. one every ms)
- process callbacks (even though some might be dropped because of limited FIFO space)
- once 2 of these have been processed (and I can calculate the rate ratio/offset to the remote clock), reduce the PWM setting to a more sensible value
Does this approach make sense, or is there a better way?
Thanks very much,
-JP
