Clock Generation for C5504.

Mushtaq Syed56993

Hi:

The following are stated in section 1.4.3.2.6, steps 2 and 6 respectively, on page 27 of SPRUGH6 :

2) Set CLR_CNTL = 0 in CGCR1.

6) Set PLL_PWRDN = 0, CLR_CNTL = 1.

However, register CGCR1 of C5504 has no such bit. This was bit 15 on VC5504. Bit 15 on C5504 has to be set to 1, according to SPRUGH6.

All references to CLR_CNTL bit apply to VC5504 and to C5504. Is this correct?

Also, should the PLL be powered down in step 2 before programming multiplier and divider registers, and then powered up in step 6?

Thanks a lot!

Cheers,

Mushtaq

over 14 years ago

0 Hyun Kim over 14 years ago

TI__Genius 14965 points

Hi,

This is a good catch. You're right about this. Document said that the CLR_CNTL doesn't exist. However It's used in the PLL set procedure.

I'll find this out and get back to you.

Regards,

Hyun

0 Hyun Kim over 14 years ago in reply to Hyun Kim

TI__Genius 14965 points

Hi,

It's confirmed that CLR_CNTL is not required in PLL setting procedure in C5505.

Regards,

Hyun

0 Mushtaq Syed56993 over 14 years ago in reply to Hyun Kim

Intellectual 750 points

Hi Hyun:

What about PLL power down?

Thanks a lot!

Cheers,

Mushtaq

Also, should the PLL be powered down in step 2 before programming multiplier and divider registers, and then powered up in step 6?

Thanks a lot!

Cheers,

Mushtaq

0 Mushtaq Syed56993 over 14 years ago in reply to Hyun Kim

Intellectual 750 points

Hi Hyun:

What about PLL power down?

Should the PLL be powered down in step 2 before programming multiplier and divider registers, and then powered up in step 6?

Thanks a lot!

Cheers,

Mushtaq

0 Hyun Kim over 14 years ago in reply to Mushtaq Syed56993

TI__Genius 14965 points

Hi Mushtaq,

That is also not a must.

Regards,

Hyun

0 Mushtaq Syed56993 over 14 years ago in reply to Hyun Kim

Intellectual 750 points

Hi Hyun:

Thanks a lot!

Cheers,

Mushtaq

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Clock Generation for C5504.