AM3359: Challenges faced in GPMC Burst mode configuration

Hi Rishabh,

I will look into it and get back to you next week.

Hi Rishabh,

Rishabh Mishra said:

We have performed multiple experiments to get the write burst mode running for now but observed that at the 2nd chip select the signal stays low and does not go high.

I am not sure I understand the issue. What do you mean by "at the 2nd chip select"? Can you please provide more details of the issue you have?

Hi Bin Liu,
We are trying to perform burst write to FPGA with a burst length of 8 words.
Here we are able to observe 2 chip selects with 4 words data being transferred to the FPGA.
I am unable to understand what is causing the burst length to divide in 2 parts of 4 words with 2 chip selects.

Here I have listed my updated DTS configuration for burst write and read.
 r4_gpmc: r4_gpmc@50000000 {
        compatible = "ti,omap-gpmc";
        reg = <3 0 0x01000000>;  /* CS3, offset 0, IO size 4*/
        interrupt-parent = <&gpmc>;
        interrupt-controller;
        interrupts = <2 IRQ_TYPE_EDGE_FALLING>, /* GPMC Wait0 active low*/
                            <3 IRQ_TYPE_EDGE_FALLING>; /* GPMC Wait1 active low*/
        #interrupts-cells = <2>;
        gpmc,num-cs = <6>;
        gpmc,num-waitpins = <2>;
        gpmc,sync-clk-ps = <10000>;
        /*GPMC Config 2 details*/
        gpmc,cs-on-ns = <0>;
        gpmc,cs-rd-off-ns = <180>; /*<130>;*/
        gpmc,cs-wr-off-ns = <190>; /*<130>;*/
        /*GPMC Config 3 details*/
        gpmc,adv-on-ns = <10>;
        gpmc,adv-rd-off-ns = <30>;
        gpmc,adv-wr-off-ns = <30>;
        gpmc,we-on-ns = <40>;
        gpmc,we-off-ns = <162>; /*<160>;*/
        gpmc,adv-aad-mux-on-ns = <0>;
        gpmc,adv-aad-mux-rd-off-ns = <0>;
        gpmc,adv-aad-mux-wr-off-ns = <0>;
        /*GPMC Config 4 details*/
        gpmc,oe-on-ns = <70>;
        gpmc,oe-off-ns = <150>;
        gpmc,oe-aad-mux-on-ns = <0>;
        gpmc,oe-aad-mux-off-ns = <0>;
        /*GPMC Config 5,6 wait-monitoring-ns details*/
        gpmc,page-burst-access-ns = <10>;
        gpmc,access-ns = <60>;
        gpmc,rd-cycle-ns = <170>;
        gpmc,wr-cycle-ns = <210>;
        gpmc,bus-turnaround-ns = <0>;
        gpmc,clk-activation-ns = <10>;
        gpmc,wait-monitoring-ns = <10>;
        gpmc,cycle2cycle-delay-ns = <0>;
        /*GPMC Boolean timing parameters*/
        gpmc,cycle2cycle-diffcsen = "false";
        gpmc,cycle2cycle-samecsen = "true";
        /*GPMC OMAP3+ & AM335x parameters*/
        gpmc,wr-access-ns = <50>;
        gpmc,wr-data-mux-bus-ns = <40>;
        /*GPMC chip select settings*/
        gpmc,burst-read = <1>;
        gpmc,burst-write = <1>;
        gpmc,burst-length = <8> ; /* 4, 8, 16 word*/
        gpmc,burst-wrap = "true";
        gpmc,device-width = <2>; /*1 for 8 & 2 for 16 bit*/
        gpmc,mux-add-data = <2>;
        gpmc,sync-read = <1>;
        gpmc,sync-write = <1>;
        gpmc,wait-pin = <1>;
        gpmc,wait-on-read = <1>;
        gpmc,wait-on-write = <1>;
        gpmc,device-nand = "false";
    };

Here is an image for your reference.

Hi TI Support Team,

We have tried working on this and observed that using these configuration only 2 locations (of 4 words) are written with proper values.
This is critical for us as we need to demonstrate the same to our customers.
Could you please check on this and let me know your observations for the same.

Awaiting your reply,
Thanks and regards,
Rishabh Mishra

Hi Bin Liu,

Let us know if you need any more inputs from us to understand it better. This is a very critical requirement, and we are trying the possible combinations in the dts still no better output.

Thanks and regards,
Rishabh Mishra

Hi Rishabh,

Sorry for the late response. I am checking internally and will get back to you.

Hi Rishabh,

I got the response from our HW expert, DMA has to be used to get 8-words or 16-words burst transfers, the burst cannot be achieved by CPU access to GPMC. But I am not sure how to implement DMA access to FPGA in your case, there is no dedicated FPGA driver in kernel, right?