C6727B EM_CS[2] signal

Tak,

The CPU is often slower than the DMA when reading a large number of locations on the asynchronous EMIF bus. This is the nature of the way the CPU does reads within the pipelined architecture compared to the nature of the DMA when programmed to read a group of locations in one Transfer Request.

There are a lot of ways the EMIF can be programmed and ways the EMIF can be accessed, even by the CPU. Different read instructions (LDB compared with LDDW, for example) will result in different operations on the bus. You may get different results with R_HOLD=0 compared with R_HOLD=7, for example.

The User's Guide should certainly be considered as being accurate. Please keep in mind the first "exception" listed at the top of Table 2-21 in the Turn-around period line.

Regards,
RandyP

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