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TMS320C6746: About clock input

Part Number: TMS320C6746


Hi all,.


I am using a 40MHz square wave for the clock.
The DSP selects the built-in oscillator at power-on, but the maximum clock frequency of the built-in oscillator is up to 30MHz.
Will the program work in this case?

Thank you very much for your help.
Suzuki

  • The maximum frequency supported by the oscillator is 30MHz. However, the device supports an externally generated 1.2V clock up to 50MHz.  See the first parameter defined in the datasheet table titled "OSCIN Timing Requirements for an Externally Driven Clock".

    You will need to configure internal PLLs and functional modules as required to account for a 40MHz reference clock frequency.

    Regards,
    Paul

  • Hi Paul.
    Thank you for your answer.

    In "TMS320C6746 DSP Technical Reference Manual Figure 7-1. PLLC Structure", it says OSCIN-Crystal-Selector. When 40 MHz is input to OSCIN, the maximum frequency is exceeded, but does it work?
    Doesn't the program not work and the setting become impossible in the state that it doesn't work normally?

    In the "TMS320C6746Data Sheet Figure 6-6. On-Chip Oscillator", OSCIN - Inverting Buffer - OSCOUT and OSCIN - Schmitt Trigger Buffer - Clock Input to PLL Clock Input to PLL.
    In reality, is there no Selector, and is the same path taken regardless of whether the square wave or XTAL is input?

    Thank you for your time.
    Suzuki

  • I was not able to find the TRM reference you mentioned above. Please provide more details where you saw 40 MHz exceeds maximum frequency.

    I found the following comment in the TRM "The valid range of multiplier values for a given OSCIN is defined by the minimum and maximum frequency limits on the PLL VCO frequency. See the device-specific data manual for PLL VCO frequency specification limits".

    The datasheet has a table titled "Allowed PLL Operating Conditions (PLL0 and PLL1)". Parameter number 4 in this table states "30 MHz (if internal oscillator is used) and 50 MHz (if external clock is used)".

    I'm not familiar with the internal structure of the oscillator implemented in this device, but I suspect it is similar to the one used in some of our older Sitara devices. If so, the path from the oscillator input to the internal reference clock is the same. The oscillators implemented in older Sitara devices have a bypass bit, but the only thing this bit does is turn off the internal feedback resistor that connects between the input and output pin. It is not necessary to turn off the feedback resistor when using an LVCMOS clock source with the older Sitara devices. It only saves a very small amount of leakage current through the feedback resistor. The frequency limitation associated with the crystal option for this device is related to oscillator amplifier gain at frequencies greater than 30 MHz. The oscillator amplifier does not have enough gain above 30 Mhz to reliably start and maintain oscillation of a crystal circuit.

    Regards,
    Paul

  • Hi Paul.
    Your explanation helped me understand the inner workings and solved my problem.
    Thank you very much.
    Suzuki