Hello community!
I have a problem with UART transmission.
I am using an AM3354 processor.
My software:
bios_6_45_01_29
ndk_2_25_00_09
uia_2_00_05_50
custom UART drivers for sys_bios.
So, 5 packets of 3 bytes are sent continuously every 4 ms with an interval of 100 μs at a speed of 3 Mb / s. Before each transmission, the line is "captured" (the signal is set to the GPIO pin HIGH) to implement the RS-485 protocol. 1) Interrupt THR is prohibited, 2) 3 bytes are put into the FIFO transfer buffer. 3) THR interrupt is enabled.
In the THR interrupt, which occurs when the TX FIFO level is below 1, a timer is started for the duration of the guaranteed transmission of all bytes. When the timer is triggered, the line is “released” (the signal is set to the GPIO pin LOW).
After some time (from 10 minutes to several hours), the data transmission "halt". Here's how. 1 out of three bytes is transmitted, the remaining 2 are not transmitted. But still, in this case, the THR interrupt, when the TX FIFO level is below 1, is generated, but the data is still in the buffer. On the next transfer, 3 bytes are again put into the FIFO transfer buffer, an interrupt is generated again, but the data remains in the FIFO buffer, then the FIFO buffer overflows and interrupts are no longer generated.
Why is it that the data is not "shifted in line" from the FIFO, but an interrupt that the FIFO transmit buffer is below 1 is generated? Why does the transfer of bytes from the FIFO buffer stop when there are many bytes to transfer in the FIFO buffer?
The first picture shows a normal transmission.
In the second picture, 1 byte was transferred and the transfer from the FIFO buffer stopped, but THR interrupts are generated until the buffer overflows.
Any help is expected…
