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I2C Slave Boot for the C6472

Graeme Parker
Expert 1265 points

Spruec6e does not have sufficient detail for C6472 I2C slave booting.

Is there a document that details exactly the structure of the data required? Where is the I2C slave address described (I'm sure it is 0x04)?

Assuming that the first byte sequence is 4, 0, 6, 0, 0, 0, 1 (slave address, length, checksum, opcode), what comes next? Is it a full boot table including frame headers and magic number (as per the EMAC boot; 0x544B, 0x01, sequence number), or just length, address, data packets?

Thanks.

  • 0
    TI__Genius 9915 points

    We don't have any other document. But please read this in tandem with i2c master boot mode. SO the only difference between the i2c master boot mode and i2c slave mode is that the host drives the i2c in the later case. Everything else is the same. So the header you mentioned above is the way host tells the DSP what is sent after wards. SO based on boot option, the next block can be boot table or boot parameter table or boot config table. Hope this helps.

     

    Thanks,

    Arun

  • 0 in reply to ArunMani
    Expert 1265 points

    So are you saying that the header I previously quoted CAN be the 1st data sent from the host to the DSP? This imples that subsequent data will just be a boot table as defined in section 6.2.2.1 of spruec6e. Trying this sequence of events does NOT result in a DSP boot!

    Or MUST I use the Boottest_Tomahawk_v1_0_0 tools to generate a .ccs file and send ALL of this data to the DSP?

     

  • 0 in reply to Graeme Parker
    TI__Genius 9915 points

    Please check the advisory 9 in the errata. According to this errata if you use silicon 1.0 and 1.1 version then you have problem using I2C slave.

     

    Thanks,

    Arun.

  • 0 in reply to ArunMani
    Expert 1265 points

    Thank you.

    We have heatsinks fitted to the DSPs I'm using at the moment (they're glued on).

    I have read the register at address 0x02A8070C) which I believe shows the revision. The register reads 0x00210091 which indicates rev 2.1; so there should not be an I2C slave boot problem. The JTAG ID reg reads 0x3009102F which confirms silicon rev 2.1

     

  • 0 in reply to Graeme Parker
    Expert 1265 points

    One last request. Which of your 6472 EVMs (or even a 3rd party's) allows I2C slave booting?

  • 0 in reply to Graeme Parker
    TI__Mastermind 30825 points

    The I2C Interface is available via a header if you have an external devices to connect as the master to perform an I2C slave boot of C6472 on the EVMs.

    Best Regards,

    Chad

  • 0 in reply to Graeme Parker
    TI__Mastermind 30825 points

    Can you put a logic analyzer on the I2C signals and capture what's being put out on the bus and share it? 

    Best Regards,

    Chad

  • 0 in reply to Chad Courtney
    Expert 1265 points

    Thanks for your post and interest in this matter. I think my question was more on the lines:

     “Do you have any C6472 Customers that uses I2C slave-booting”

     We simply believe that it’s not possible. We are not the brightest people in the World, but this should be so easy as it’s so simple. I am happy to ship an EVP6472 – www.ev6472.com – and you can have it for good if you can make it boot the second DSP.

     

    The second question could be:

    “Have TI ever tested one EVM6472 booting another EVM6472 on the slave I2C?”

    Maybe this is a question of eInfochips and I will ask them.