I wrote a multi-core program. When 128KB cache is used, the result is correct, but when 256KB cache is used, the result is wrong. I would like to ask how I can solve this problem.
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I wrote a multi-core program. When 128KB cache is used, the result is correct, but when 256KB cache is used, the result is wrong. I would like to ask how I can solve this problem.
Hi Zhong,
Please refer this document https://www.ti.com/lit/ug/sprugy8/sprugy8.pdf for DSP cache user guide. Please refer page 34 and 35 for examples.
If the problem still persists, kindly share the C66x linker command file and CSL command sequence for enable caching.
Thanks & regards,
Rajarajan U