Part Number: TDA4VM
Hi,
We need to read the ADC data of 4x AWRs into the TDA4VM via CSI-2 interface. Since the TDA4VM has only 2x CSI-2 modules, an aggregation of two AWRx CSI-2 outputs into one single CSI-2 output is required (e.g. via using a FPGA module). For this, I need to know whether the bit rate of TDA4VM CSI-2 module is sufficient ?
Given the following conditions:
- For each AWR, 4RXs are used
- In each single chirp, there's 1024 samples and the chirp repetition interval is 30µs.
- Each sample has 16 bits (or 2bytes)
If my calculation is correct, (for simplicity assumed 1Rx takes 1 lane) then the minimum required CSI-2 bit rate per lane per AWR is:
(1024samples * 2bytes) / 30µs = 546Mbps per lane. After aggregation of 2x AWRs, the data rate is 546Mbps * 2 = 1092Mbps per lane (overhead of CSI-2 protocol is not yet considered)
So my questions are:
1) Is my calculation correct ?
2) Can the TDA4VM CSI-2 lane support the data rate of 1092Mbps per lane ?
3) What is the maximum data rate per lane that the TDA4VM CSI-2 module can support ?
4) and for understanding, how does the max. 750 MHz relate to 2.5Gbps (as given in the data sheet) ?
many thanks.
BL
