DRA829V: DRA829 Enabling of PCIe Ref CLK in QNX

Divyanshu kumar

Part Number: DRA829V

Hi Team,

In EVM External Clock generator is used for the PCIe Reference clock, but In our Custom Board we are using internal SOC clock for generating the Reference clock at 'PCIE_REFCLK0P and PCIE_REFCLK0N' pin. So we want to know the changes Required in QNX to Enable the Internal Reference clock of the PCIE.

we have tried the below Register configuration in src/hardware/startup/boards/j721e/evm/hw_init.c but didn't get the Reference clock output from the Processor.

J721E_CTRLMMR_LOCK2_KICK0-0x68EF3490

J721E_CTRLMMR_LOCK2_KICK1-0xD172BC5A

CTRLMMR_PCIE_REFCLK0_CLKSEL -0x00000100
CTRLMMR_PCIE_REFCLK1_CLKSEL -0x00000101
CTRLMMR_PCIE_REFCLK2_CLKSEL -0x00000100
CTRLMMR_ACSPCIE0_CTRL- 0x01000000

please suggest anything missed, or any other register also required to configure.

Regards

Divyanshu

over 4 years ago

0 Divyanshu kumar over 4 years ago

Intellectual 280 points

Hi Team,

Any update on above queries waiting for your feedback.

Regards

Divyanshu

0 KB over 4 years ago in reply to Divyanshu kumar

TI__Guru*** 132231 points

Hi Divyanshu,

Can you please comment on whether the QNX PCIe Framework offering is in use, or if this is a custom framework that is being developed.

Thanks,

0 Divyanshu kumar over 4 years ago in reply to KB

Intellectual 280 points

Hi kb,

We are using qnx pcie framework offering.

We got a pre release from qnx. and same we validated on EVM.

For our custom board the pcie reference clock should be provided by the SOC, since we didn't use external clock generator which is used in EVM.

We are doing modification in BSP for our custom board to validate the same in our custom board.

Thanks

Divyanshu

0 KB over 4 years ago in reply to Divyanshu kumar

TI__Guru*** 132231 points

Hi Divyanshu,

Please see the below thread for a similar effot which was done on Linux.

(+) Compiler/TDA4VM: Are there write protection restrictions on the operation of the CTRLMMR_PCIE_REFCLK1_CLKSEL register? - Processors forum - Processors - TI E2E support forums

Regards,

0 Divyanshu kumar over 4 years ago in reply to KB

Intellectual 280 points

Hi Kb,

Thanks for the link.

we have already looked into the above link earlier. From the patch we not able to get what are the register of Processor need to modify to get reference clock accept the register which i Mentioned above.

It would be Better if you could provide the list of registers need to modify to get Internal Reference Clock.

Regards

Divyanshu

0 jian35385 over 4 years ago in reply to Divyanshu kumar

TI__Mastermind 23125 points

Divyanshu,

Besides enabling the ACSPCIe clock buffers, you also need to:

Select SERDES output as the input to the clock buffers

This sets the mux to the clock buffer input. I wrote an overview of the steps:

https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1004565/faq-tda4vm-tda4vm-dra829v-routing-pcie-reference-clock-externally?tisearch=e2e-sitesearch&keymatch=routing%20refclk%20externally#

could you take a look and see if it give you all the details for QNX. If not, please reply back I will give you register names.

Jian

+1 Divyanshu kumar over 4 years ago in reply to jian35385

Intellectual 280 points

Hi Jian,

Thanks for providing the details

one things I not able to understand for doing the below changes

Select SERDES output as the input to the clock buffers

which SERDES registers need to modify i got the below register from TRM is that correct register and value.

CMN_PLLLC_CLK1_PREG__CMN_PLLLC_LOCK_
CNTTHRESH_PREG - 0x102e0001

Regards

Divyanshu.