McBSP Connection to Unusual(?) PCM Device

Chris

Although I have not tried this, I do believe that the hardware can be setup for this configuration. CLKX can be configured as external and as the source for the Sample Rate Generator which will generate the SYNC signal. 

I do not believe that the current Linux driver supports this mode.  

  Paul

It looks to me like I should be able to configure CLKR as an input and have CLKX be an output that mirrors CLKR by having CLKR be the input to the SRG's CLKG circuitry.

I have attempted to configure the McBSP1's SRG clock generation to have mcbsp1_clkr be the input clock to the SRG, by doing the following:

1. Set SRGR2[13].CLKSM to 0 to select mcbsp1_clkr
2. Set PCR[7].SCLKME to 1 to select external clock
3. Set PCR[9].CLKXM to 1 to have mcbsp1_clkx be an output of SRG's CLKG
4. Cleared PCR[8].CLKRM to 0 to have mcbsp1_clkr be an input.

This is shown in the following output:

--------------------------------- McBSP1 ---------------------------------
DRR2:  0xdbef2140
DRR1:  0x0000
DXR2:  0x0000
DXR1:  0x0000
SPCR2: 0x02f5
SPCR1: 0x0030
RCR2:  0x0041
RCR1:  0x0040
XCR2:  0x0041
XCR1:  0x0040
SRGR2: 0x000f
SRGR1: 0x0700
PCR0:  0x0a8f
XCCR:  0x1008
RCCR:  0x0809
---------------------------------------------------------------------------

The pinmuxing on the mcbsp1_clkr and mcbsp1_clkx as given by the OS are:

mcbsp1_clkr:name: mcbsp1_clkr.mcbsp1_clkr (0x4800218c/0x15c = 0x0100), b y21, t NA
mcbsp1_clkr:mode: OMAP_PIN_INPUT | OMAP_MUX_MODE0
mcbsp1_clkr:signals: mcbsp1_clkr | mcspi4_clk | NA | NA | gpio_156 | NA | NA | safe_mode
mcbsp1_clkx:name: mcbsp1_clkx.mcbsp1_clkx (0x48002198/0x168 = 0x0000), b w21, t NA
mcbsp1_clkx:mode: OMAP_PIN_OUTPUT | OMAP_MUX_MODE0
mcbsp1_clkx:signals: mcbsp1_clkx | NA | mcbsp3_clkx | NA | gpio_162 | NA | NA | safe_mode

I drive the mcbsp1_clkr with a 2.048MHz clock, but the clock doesn't appear on the mcbsp1_clkx pin.  There is some feed through of ringing onto the mcbsp1_clkx pin, but it's driven continuously high.

Is there more register configuration that I need to do?  Did I misinterpret something?

Thanks in advance for your help.

Chris

Using CLKR as the clock source to generate CLKX (which is looped back from the i/o) to drive the transmitter would probably add to much latency to the transmit data.

I think the best option is use CLKX as an input (driven by the PCM device) to drive the SRG (and transmitter). The SRG would generate FSX  and the transmitter would drive the data. My only concern is the delay in generating FSX.

  Paul

Paul,  Thanks so much for your quick reply.

I wasn't actually planning on using the output from CLKX to clock the data.  I was planning on using CLKR as driven by the PCM device, but maybe I don't have that much control.  Is that not possible?

I actually just wanted to look at the output of CLKX to make sure it was actually getting the CLKR signal and was generating CLKG properly so it could generate FSX from it.

It seems to me that at only 2.048MHz the delay wouldn't be that great as a fraction of the pulse width, since I think those clocks can go much higher in frequency.

Would the delay actually be any greater generating FSX from CLKR than CLKX?

Is there anything else I need to do to get CLKX to show up as a clone of CLKR?

Thanks again,

Chris

Again, much appreciated, Paul...

I am getting frame sync out of FSX when inputting the clock on CLKX.  I am now also getting the clock out of CLKR, but I may have been testing in incorrectly before.

- Chris

Krunal

Please see my answer in the other thread Re: TIWL1271 and MCBSP interface on OMAP3530EVM.

  Paul