Disabling cash on SL2RAM

khaled,

By what means do you clearly see that the SL2RAM is being cached?

In most cases, you will get better performance if you do allow caching and do the invalidate and writeback commands. But there are cases where this is not desired. Since you will be more likely to want caching for external DDR2 memory, it is best not to turn cache off completely, but to control it on a more granular quantity of memory.

The MAR bits are used to enable or disable caching on 16MB boundaries. Please search the datasheet and the C64x+ Megamodule Reference Guide for references to "MAR". These sections will explain how it is used and where the MAR registers are located. BIOS has API support for the MAR bits to control caching.

Regards,
RandyP

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Randy,

To answer your question "By what means do you clearly see that the SL2RAM is being cached?", CCS color code the memory light blue when its cashed. CCS/memory viewwer has the option to view cashed L1D, L1P, and LL2 memory.

As for the MAR bits. The MAR bits control the cashing of the external memory 0x1000 0000 to 0x15FF FFFF and 0xE000 0000 to 0xFFFF FFFF.

What I need is to disable the cash of SL2RAM [ base = 0x002BF000, length = 0x1000]. I'm using this section of the memory to pass data between the 6 cores and problems are occurring when more than 1 core tries to access the same memory location.

khaled.

The address ranges from 0x1000 0000 to 0x15FF FFFF are internal global addresses. For a given core, one set for that core are equivalent to the internal local addresses from 0x0000 0000 to 0x00FF FFFF.

MARs control caching in these internal global address ranges. You can use the global address range for SL2RAM and have caching turned off for it. This would turn off caching for all of the internal addresses in that range as described in the datasheet.

The internal local address range for the same memory will not be affected by the respective MAR bits.

This is a confusing feature of these C64x+ multi-core devices, but it can also be a powerful feature to use.

Regards,
RandyP

Thank you for the info, I missed that part :-)

So I checked the BIOS and ALL MAR registers are set to "0" i.e. not cached. But, using CCS memory viewer, the SL2RAM is cached!

Could it be due to the DSP chip it self C6472, or it has something to do with using local address range versus global address range?

khaled

My assumption is that you will see different caching effects if you view SL2RAM at 0x10200000 rather than 0x00200000. Does that explain the discrepancy? The MAR bits will not affect the internal local address at 0x00200000.

Regards,
RandyP

Khaled, if you don't want data in SL2RAM to be cached, have you considered disabling L1D cache?  If you wanted, you could also disable L1P although I can't think of a reason why this would be useful.

By default, L1D is enabled, but you can disable it either in your RTSC Platform or at runtime using BIOS/CSL APIs.

Regards,

Shreyas