AM5728: IPU GPIO interrupt

Hi,

SDK: ti-processor-sdk-rtos-am57xx-evm-04.03.00.05/

Project based on ti-linux-ipc-examples\ex02_messageq, and the program always crash at below code:

Log_print1(Diags_USER1, "VirtQueue_startup: VDEV status: 0x%x\n",
              Resource_getVdevStatus(VIRTIO_ID_RPMSG));
    Log_print0(Diags_USER1, "VirtQueue_startup: Polling VDEV status...\n");
    while (Resource_getVdevStatus(VIRTIO_ID_RPMSG) != VRING_BUFS_PRIMED);
    Log_print1(Diags_USER1, "VirtQueue_startup: VDEV status: 0x%x\n",
              Resource_getVdevStatus(VIRTIO_ID_RPMSG));

    InterruptProxy_intRegister(hostProcId, &intInfo, (Fxn)VirtQueue_isr,
            (UArg)NULL);
    Log_print0(Diags_USER1, "Passed VirtQueue_startup\n");

Below is GPIO code:

GPIO_PinConfig gpioPinConfigs[] = {
    GPIO_DEVICE_CONFIG(6, 6)  |GPIO_CFG_IN_INT_BOTH_EDGES| GPIO_CFG_INPUT,
};

GPIO_v1_Config GPIO_v1_config = {
    .pinConfigs = gpioPinConfigs,
    .numberOfPinConfigs = sizeof(gpioPinConfigs) / sizeof(GPIO_PinConfig),
};

/* 0x4a003400U+0x20000000U */
CSL_FINS(regVal, CONTROL_CORE_PAD_IO_PAD_MCASP1_AXR15_MCASP1_AXR15_MUXMODE, 0x0000EU);
((CSL_padRegsOvly) PHYSTOVIR_REG_40000000(CSL_MPU_CORE_PAD_IO_REGISTERS_REGS))->PAD_MCASP1_AXR15 = regVal;

/* GPIO initialization */
GPIO_init();

GPIO_setCallback(0, AppGpioCallbackFxn);
GPIO_enableInt(0);

// GPIO_soc.c
GPIO_v1_hwAttrs_list GPIO_v1_hwAttrs = {
...
{
#ifdef _TMS320C6X
       CSL_DSP_GPIO6_REGS,
       OSAL_REGINT_INTVEC_EVENT_COMBINER,
#elif defined(__ARM_ARCH_7A__)
       CSL_MPU_GPIO6_REGS,
       66,
#else
#ifdef PHYSTOVIRT_EANBLE
       PHYSTOVIR_GPIO6_REGS, // 0x6805d000U
#else
       CSL_IPU_GPIO6_REGS,
#endif
       49,
#endif
       0,
       CSL_XBAR_GPIO6_IRQ_1,
       0
    },
...
};


// GPIO_app.c
GPIO_PinConfig gpioPinConfigs[] = {
    GPIO_DEVICE_CONFIG(6, 6)  |GPIO_CFG_IN_INT_BOTH_EDGES| GPIO_CFG_INPUT,
};

GPIO_v1_Config GPIO_v1_config = {
    .pinConfigs = gpioPinConfigs,
    .numberOfPinConfigs = sizeof(gpioPinConfigs) / sizeof(GPIO_PinConfig),
};

/* 0x4a003400U+0x20000000U */
CSL_FINS(regVal, CONTROL_CORE_PAD_IO_PAD_MCASP1_AXR15_MCASP1_AXR15_MUXMODE, 0x0000EU);
((CSL_padRegsOvly) PHYSTOVIR_REG_40000000(CSL_MPU_CORE_PAD_IO_REGISTERS_REGS))->PAD_MCASP1_AXR15 = regVal;

/* GPIO initialization */
GPIO_init();

/*  */
CSL_xbarIrqConfigure (CSL_XBAR_IRQ_CPU_ID_IPU1, (49 - 22), CSL_XBAR_GPIO6_IRQ_1);
// IntXbar_connectIRQ(49, CSL_XBAR_GPIO6_IRQ_1);

GPIO_setCallback(0, AppGpioCallbackFxn);
GPIO_enableInt(0);