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Original question:

[FAQ] TDA4VM: On 7.3/8.0 SDK how to reduce DDR speed to 3733 MTS

TDA4VM: Why the increase in DDR frequency is unsuccessful?

SandalHao
Intellectual 665 points
Part Number: TDA4VM

Hi,

The DDR frequency of SDKV7.3 is 2133MHZ (4266 MTS). We want to increase it to 2347MHZ(2133*1.1).

So we  use the JacintoTm 7 DDRSS Register Configuration Tool and modify it to generate dtsi file.

/dts-v1/;

#include "k3-j721e-som-p0.dtsi"
//#include "k3-j721e-ddr-evm-lp4-4266.dtsi"
#include "k3-j721e-ddr-evm-lp4-4694.dtsi"
#include "k3-j721e-ddr.dtsi"

After recompiling uboot, enter Linux and execute the k3conf command and find the following log:

root@TDA4-Board:~# k3conf dump clocks 47
|--------------------------------------------------------------------------------|
| VERSION INFO                                                                   |
|--------------------------------------------------------------------------------|
| K3CONF | (version v0.1-45-g79f007c built Sat Apr 10 00:45:34 UTC 2021)         |
| SoC    | J721E SR1.0                                                           |
| SYSFW  | ABI: 3.1 (firmware version 0x0014 '20.8.5--v2020.08b (Terrific Lla)') |
|--------------------------------------------------------------------------------|

|---------------------------------------------------------------------------------------|
| Device ID | Clock ID | Clock Name                 | Status          | Clock Frequency |
|---------------------------------------------------------------------------------------|
|    47     |     0    | DEV_DDR0_DDRSS_VBUS_CLK    | CLK_STATE_READY | 1000000000      |
|    47     |     1    | DEV_DDR0_PLL_CTRL_CLK      | CLK_STATE_READY | 500000000       |
|    47     |     2    | DEV_DDR0_DDRSS_DDR_PLL_CLK | CLK_STATE_READY | 782336000       |
|    47     |     3    | DEV_DDR0_DDRSS_CFG_CLK     | CLK_STATE_READY | 125000000       |
|    47     |     4    | DEV_DDR0_DDRSS_IO_CK_N     | CLK_STATE_READY | 0               |
|    47     |     5    | DEV_DDR0_DDRSS_IO_CK       | CLK_STATE_READY | 0               |
|---------------------------------------------------------------------------------------|

root@TDA4-Board:~#

It seems that the frequency has not increased but decreased. DDR can reach 2166MHZ before changing the frequency.

I would like to ask what went wrong?

Thanks!

  • 0
    TI__Guru**** 163810 points

    Hi,

    Apologies for the long delay. 4266 MTS will lock DDR DPLL at 1066 GHz. Is that functional on your setup?

    - Keerthy

  • 0 in reply to Keerthy J
    Intellectual 665 points

    Increase the frequency to 2347 MHz. Do I need to change other places besides DTS? Can you tell me where I need to change?

  • 0 in reply to SandalHao
    TI__Guru**** 163810 points

    Hi,

    We have never tried 4694MTS from the TI side.

    For 3733 MTS the DDR PLL will lock at 933 MHz. so arch/arm/dts/k3-j721e-ddr-evm-lp4-3733.dtsi has:

    #define DDRSS_PLL_FHS_CNT 10
    #define DDRSS_PLL_FREQUENCY_1 933000000
    #define DDRSS_PLL_FREQUENCY_2 933000000

    Similarly for 4266MTS DDR PLL Locks ar 1066 MHz.


    #define DDRSS_PLL_FHS_CNT 10
    #define DDRSS_PLL_FREQUENCY_1 1066500000
    #define DDRSS_PLL_FREQUENCY_2 1066500000

    Now what is your DTS file containing for the above #defines?

    No other changes needed apart from DTS changes.

    Best Regards,
    Keerthy