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TDA4VM: DED in VIM RAM

Rizwan Ahmad
Intellectual 676 points
Part Number: TDA4VM

Hi,

We have observed that upon an IRQ interrupt, the IRQVEC register is not returning the expected IRQ vector register which was initialized correctly earlier. The value that IRQVEC register shows is same as the contents of DEDVEC register, the description of which tells that there is a double bit error detected in VIM IRQ vector RAM.

How can we prevent this double bit error. We are facing this on MCU domain R5 cores.

Any insights on this topic will be appreciated.

Rizwan

  • 0
    Intellectual 676 points

    PS: We have also observed that after power on reset the VIM IRQVEC and DEDVEC registers do not show the default zero value as mentioned in the TRM.

  • 0 in reply to Rizwan Ahmad
    TI__Expert 6870 points

    Hi,

    Rizwan Ahmad said:
    the IRQVEC register is not returning the expected IRQ vector register which was initialized correctly earlier

    Can you give more details about the earlier environment where it was working correctly and it's delta with new environment.

    Also, can you mention the SDK, OS and example used for this.

    As mentioned in the TRM " If a double-bit error occurs while trying to load a vector, then the R5FSS_VIM_DEDVEC register is used to provide the default vector for the coreN_IRQADDRV signal, the R5FSS_VIM_IRQVEC register, and the R5FSS_VIM_FIQVEC register ".

    Have you tried the actions suggested.

    Also, go through Table 6-639. R5FSS_VIM_DEDVEC Register Field Descriptions:

  • 0 in reply to ANUBHAV AKASH
    Intellectual 676 points

    Hi Anubhav,
    thanks for your reply.

    It is important for us to avoid a Double Bit Error in VIM RAM and we are interesting in knowing if there is any VIM initialization step we are missing. The interrupt that arrives is coming from a Timer Module. Instead of jumping to its vector address, CPU jumps to the DEDVEC address. How can we ensure that at all times, the correct vector address is picked, the one which was configured during VIM initialization.

    Rizwan