AM6442: L2 cache partitioning

Andrea Tessadri

Intellectual 567 points

Part Number: AM6442

Is there any way to control L2 cache partitioning within A53 cluster ?

I will be working with Linux RT SDK.

Thank you in advance

Andrea

over 4 years ago

+1 Pekka Varis over 4 years ago

TI__Mastermind 27050 points

Andrea,

No there is not. The Cortex A53 cluster (2 cores in AM6442 case) does not allow SW to manage the cache allocation between the cores beyond marking memory pages either cacheable or not.

On AM6442 the four Cortex R5 cores and usage of TCM and OCRAM memory are intended for the applications that require microsecond level real-time guarantees.

Pekka

0 Andrea Tessadri over 4 years ago in reply to Pekka Varis

Intellectual 567 points

Thanks a lot Pekka for your quick reply.

I found in AM6442 TRM the description of how to use TCM but I cannot find any reference to OCRAM.

0 Pekka Varis over 4 years ago in reply to Andrea Tessadri

TI__Mastermind 27050 points

Sorry about that, with OCRAM I'm referring to the on chip shared SRAM. The AM64x uses the term MSRAM in the TRM and then OCSRAM in the datasheet. Some older devices such as AM57x used the term OCRAM for similar on chip SRAM.

Pekka

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AM6442: L2 cache partitioning