AM5706: Bus Error occurred on GPMC during access to FROM

Hideaki-san,

Section 15.4.6.1 How to Set GPMC Timing Parameters for Typical Accesses has some timing diagrams to show the expected timing relations.  Table 15-489 GPMC Timing Parameters for Async Single Write in particular seems to fall under customer's use case.

I noticed CsWrOffTime should be WeOffTime + 1, it is right now set as 4 cycles but should be 5.

WrCycleTime is WeOffTime + AccessCompletion. AccessCompletion should follow nCS de-assertion time, so WrCycleTime should be programmed with the same value as CsWrOffTime. 

If a higher cycle time works, that could mean the memory device required higher AC timing characteristics.  Are the values set correctly based on the memory device timing?

Thanks & Regards,

Shiou Mei

Hi Shiou Mei,

Thank you for your reply. They’ve tried your suggestion, but the issue has not been solved.

As you mentioned, they changed CsWrOffTime from 4 to 5 and tried it to run, but the symptom did not improve.

Also, they tried below.
After changing CsWrOffTime from 4 to 5,

• WrCycleTime = 5 since you mentioned that “WrCycleTime” needs to be programmed with the same value as CsWrOffTime”.
• WrCycleTime = 6 to be longer than de-assert time, because they’re using the shifted nCS by half a clock (CSEXTRADELAY enabled).

but neither seemed to improve the symptom.

Also in the case of CsWrOffTime is changed from 4 to 5, it seems that the symptom is improved by changing WrCycleTime to 7, just like when it remains at 4.

They'd like to clarify the cause of this phenomenon. Are there any other conditions that seem to be related?

This problem occurs only in the write access. They think that the AM5706 is just issuing and ending, because the external WAIT control is not used. However. It gets into error state (debugger will be frozen.) after the write access waveform appears.

Could you please help them ? Do you have any idea to solve this issue ?

Thanks and regards,
Hideaki

Hi Shiou Mei,

Thank you for your reply, but sorry for backing to this thread. Could you please confirm their setting below ?

They’re using the FROM “MT28EW512ABA1LJS-0SIT” by Micron.

They had already recognized the descriptions in TRM which you suggested. They think that “WrCycleTime = WeOffTime + AccessCompletion = WeOffTime + 1” is the key point for the bus error issue at this time.

Since they are using GPMC as Async access mode (No external wait) with Address Non-mux, they didn’t consider about the setting “ADVONTIME” and “ADVWROFFTIME”.

Do the settings of these parameters impact the address non-mux mode also ?

When they set “WrCycleTime-1” into the “ADVONTIME”, the issue doesn’t occur.

Is their setting correct ? They want to confirm with you if the issue was cased by the setting of “ADVONTIME”.

Thanks and regards,

Hideaki

Hideaki-san,

ADV is address valid signal so yes it should be programmed even in asynchronous mode.  ADVONTIME should be set to Address Valid setup time on the device side; setting it to WRCYCLETIME-1 seems too high.  Please reference the Micron device DM to confirm the valid number to program.

Thanks & Regards,

Shiou Mei