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AM4376: DDR access issue

Koichiro Tashiro
Mastermind 22945 points
Part Number: AM4376


Hi,

My customer reported DDR3L access issue on their board.
The failure is observed more than 10 boards in the market (total 11k boards were released).
The issue happens just after boot-up and the system stops during DDR accesses.

The customer checked the failing boards and found there are differences in DQS signal voltage swing.
On normal boards, the voltage swing is ~700mV (0.684V center).
On failing boards, some DQS signals show voltage swing ~1.344V(0.684V center)
Please see attached excel sheet for waveform comparison in details.
DDR_issue.xlsx
The failing boards show 100% failure rate (i.e. the issue is reproduced 100%).
But these boards were working fine before. Then these boards suddenly showed failing behavior.

Are there any similar issues reported before?
What is potential root cause of the issue?
Any debug recommendation?

Thanks and regards,
Koichiro Tashiro

  • 0
    TI__Guru* 89485 points

    I'm not sure what could be going wrong here.  It almost seems like the controller is in a completely different DDR mode.  Can you have the customer dump the EMIF registers on a failing (after a failure) and a passing board (after DDR initialization)?  0x4C000000-0x4C00031C

    Regards,

    James

  • 0 in reply to JJD
    TI__Mastermind 22945 points

    Hi James,

    Please find below EMIF register dump.
    Column B is working and Column B is failing board.
    As you can see most of configurations are the same, but some PHY_STS registers are different.
    I guess they are leveling results. 

    EMIF_Registers.xlsx

    Thanks and regards,
    Koichiro Tashiro

  • 0 in reply to Koichiro Tashiro
    TI__Mastermind 22945 points

    Hi James,

    Customer did simple Write/Read tests on the failing board (the same board above).
    And found data byte2(bit[23:16]) were corrupted.
    Waveforms were also checked and it seems DQS signals are not working properly in Read accesses.
    Please see attached excel sheet in details.

    ReadWriteTest.xlsx

    Thanks and regards,
    Koichiro Tashiro

  • 0 in reply to Koichiro Tashiro
    TI__Guru* 89485 points

    Thanks for the details.  I checked the register dump, and i don't see any major issues in the differences.  There certainly seems to be some difference in byte2 (maybe because of trace length differences), but the training looks to be converging to satisfactory values.

    If they are having issues with only reads, then that is most likely a problem with the memory itself, as the memory will drive DQS on reads.  Do all failing boards show only read failures?  If this is the case, there could be an assembly issue, or the DDR memory itself has failed.  I would have them replace the memory on a couple of boards to see if that resolves the issue.

    If they ever see write issues, then we would focus our attention on the processor, as that would be driving the DQS on writes.

    Regards,

    James

  • 0 in reply to JJD
    TI__Mastermind 22945 points

    Hi James,

    Customer already tried to replace the memory on the failing board, but it did not solve the issue. In fact the data I attached in previous post were taken with the failing board with DDR replaced.
    You are right in the point DQS signals are driven by the memory in read, but customer wonders signal behavior is also affected by receiver (AM4376).

    Customer checked another failing board and found write DQS signal showed low voltage level.
    And the same board showed strange waveform in read, too. The center voltage level does not aligned between DQS2 and DQSN2.
    Please see attached excel for details.
    ReadWriteTest(No8).xlsx

    Thanks and regards,
    Koichiro Tashiro

  • 0 in reply to Koichiro Tashiro
    TI__Guru* 89485 points

    Still not sure what is going on.  It is strange that these boards worked before and only byte2 is giving issues.  i have a few more questions.

    -Are they seeing this issue after a POR (cold boot)?  If so, can they try a warm boot and see if they see the same issue.  This would help to determine if any power up issues are possibly affecting the DDR initialization or training

    -do they have VTT implemented on the board?  If so, is the VTT regulator enabled before DDR init and training?  Can you show those schematics? 

    Regards,

    james