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DRA821U: Bus parity/ECC for R5FSS

Yu Kui
Intellectual 695 points
Part Number: DRA821U
Other Parts Discussed in Thread: DRA821

Dear experts,

For interconnection in R5F core, the bus parity/ECC is not supported as mementioned in DRA821U TRM, as attached below.

But in Cotex-R5 Technical Reference Manule(DDI0460D_cortex_r5_r1p2_trm.pdf), bus ecc is supported.

Why is this feature not implemented in DRA821U?

Is there any failure during data transmission, how to avoid this kind of faults?

  • 0
    TI__Guru** 109201 points

    Hi,

    The interconnect architecture (CBASS) on the DRA821 device, includes (among others) the below diagnostics which provides diagnostic coverage for the bus.

    • CBA1 - Parity of control and address signals
    • CBA2 - ECC of data signals
    • CBA3 - Duplication of critical control signals
    • CBA4 - Override register parity

    The Safety Manual can be referenced for details.

    Regards,

    kb

  • 0 in reply to KB
    Intellectual 695 points

    Hello, 

    I think the CBASS is the connection between R5FSS  and other subsystems. I want to know the internal connection in R5F. the follow picture attached is the interconnection from ARM R5 TRM. If there is any faults in AXI and AHB bus, how to find and avoid it?

  • 0 in reply to Yu Kui
    TI__Guru** 109201 points

    Hi,

    My understanding (from internal discussions) is the lines in the diagram below are not internal AMBA busses in the R5 sub-system, they are only internal logic connections. 

    The R5 bus parity/ECC feature is only applicable to the external AXI/AHB interfaces as parity/ECC are appended/terminated right on the boundary of the R5.

    Regards,

    kb

  • 0 in reply to KB
    Intellectual 695 points

    In the TRM R5F chapter, the mentioned un-supported features - bus ecc/parity is for what?

  • 0 in reply to Yu Kui
    TI__Guru** 109201 points

    The DRA821 TRM note is referring to the below build parameters called out in the ARM R5 TRM

    Regards,

    kb

  • 0 in reply to KB
    Intellectual 695 points

    So, there are two build parameters for AXI and AHB buses . Then in DRA821, the build parameter is no AXI/AHB bus ecc parity?

  • 0 in reply to Yu Kui
    TI__Guru** 109201 points

    Correct.  In DRA821 the optional ARM R5F AXI Bus ECC/Parity and AHB Bus ECC/Parity are not included. 

    The interconnect architecture (CBASS) on the DRA821 device, includes (among others) the below diagnostics which provides diagnostic coverage for the bus.

    • CBA1 - Parity of control and address signals
    • CBA2 - ECC of data signals
    • CBA3 - Duplication of critical control signals
    • CBA4 - Override register parity

    The Safety Manual can be referenced for details.

    Regards,

    kb