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In the DDR Interface Description (SPRÙFI2.pdf, march 2009) page 12. Subsection 2.1 says:
VCLK is the configuration bus/peripheral system interfaces clock (PLLC1SYSCLK4)
wihch then would mena it is programmable.
The section 2.1.1 below says :
VCLK is clocked at a fixed divider ratio of PLL1. This divider is fixed at 4, that is, VCLK is clocked at a
frequency of PLL1/4.
What is correct ?
Best regards
Enst
