AM5748: GPMC Interface with external Serial controller IC through IPU1

Janardan,

Do you have any interrupts or cache enabled?  Might be good to disable them for the debug.  Moreover, can you try configuring GPMC bus timing from DSP1 or ARM, and configure serial controller IC via IPU and see how the reads behave?  Did you see any errors in the GPMC status register? 

Best Regards,

Shiou Mei

Hi Mei,

Thanks for the quick response. As of your suggestion I have disabled cache and interrupts, Configured GPMC bus from ARM A15/DSP1 and tried Serial controller register write and readback from IPU1 but the results are same as seen before. The register readbacks are unsuccessful. No errors are seen in status registers.

Thanks,

Janardan M

Janardan,

Have you compared the read data or probe the signals to understand what could be causing the issues?  Will be good to confirm the signals are toggling as expected and the serial controller IC is returning correct data when accessed from IPU1.  Does the IC offer any error status registers?

Best Regards,

Shiou Mei

Janardan,

Can you also compare the GPMC waveforms when accessing from a different CPU than the IPU?

Thanks,
Kyle

Hi all,

I have captured some waveforms. Details are as below. 

• Configured GPMC bus from DSP1. Tried reading and writing Serial Controller registers through A15 core. This is working.

Sequence of operation:

1. Write register Address  to write
2. Write register Data
3. Write register address to read 
4. Read register data

Below Image shows the waveforms. CS, write enable are low  and read enable is high while write access. CS, read enable are low and write enable is high while read  access. This is as expected.

• Configured GPMC bus from DSP1. Tried reading and writing Serial Controller registers through IPU1 core. This is not working.

Sequence of operation:

1. Write register Address  to write
2. Write register Data
3. Write register address to read 
4. Read register data

Below Image shows the waveforms. CS, write enable are low and read enable is high while write access. CS, read enable and write enable is high while read  access. This behaviour is unexpected and inconsistent.

Below is the code used. Please let me know if something is being done wrong.

/*Resource Table node*/
#define IPU1_GPMC_Mem_Virtual   (0x16000000) 
#define IPU1_GPMC_Mem_Physical  (0x14000000)
   {
        TYPE_DEVMEM,
        IPU1_GPMC_Mem_Virtual, IPU1_GPMC_Mem_Physical,
        SZ_16M, 0, 0, "Zilog_Mem",
    },
    
/*code snippet*/

#define GPMC_CS_1_16MB_START_ADDR_TX_Zilog   0x16000000
#define GPMC_CS_1_16MB_START_ADDR_RX_Zilog   0x16000400

volatile uint8_t * Z85_GPMC_CH_A_REG  = (volatile uint8_t *) (GPMC_CS_1_16MB_START_ADDR_TX_Zilog+1);//channel A command
volatile uint8_t * Z85_GPMC_CH_A_DATA  = (volatile uint8_t *) (GPMC_CS_1_16MB_START_ADDR_TX_Zilog+3);//channel A data

void z85_Register_write(uint8_t Reg_Address,uint8_t Reg_Value,uint8_t CHANNEL){


    if(CHANNEL==0){
        *(Z85_GPMC_CH_A_REG)=Reg_Address;
        FDelay(1000);
        *(Z85_GPMC_CH_A_REG)=Reg_Value;
        FDelay(1000);
    }else{
        *(Z85_GPMC_CH_B_REG)=Reg_Address;
        FDelay(70);
         *(Z85_GPMC_CH_B_REG)=Reg_Value;
        FDelay(70);
    }
}

uint8_t z85_Register_read(uint8_t Reg_Address,uint8_t CHANNEL){

   uint8_t Reg_Value=0;
   if(CHANNEL==0){

       *(Z85_GPMC_CH_A_REG)=Reg_Address;
       FDelay(70);
       Reg_Value=  *(Z85_GPMC_CH_A_REG);
       FDelay(70);
       return Reg_Value;
   }else{
       *(Z85_GPMC_CH_A_REG)=Reg_Address;
       FDelay(70);
        Reg_Value=  *(Z85_GPMC_CH_A_REG);
        FDelay(70);
        return Reg_Value;
   }

}

Please let me know is there any issue in the way the memory is being accessed through IPU.

Thanks,

Janardan M

Janardan,

Can you help capture actual scope waveforms?  Could your logic analyzer resolution be too low to see all toggles correctly?

Thanks & Regards,

Shiou Mei