What is maximum frequency of input to DDR2 controller on TMS320DM6437 processor?

Timothy Murtaugh

Other Parts Discussed in Thread: TMS320DM6437

Hello,

I'm using CCS version 4.2.0.10018 and SYS/BIOS 6.30.2.42 to develop an application for the TMS320DM6437. This processor is on a custom board that we have developed.

We are using DDR2 SDRAM that is compliant with the DDR2-800 specification. I'm attempting to program the DDR2 interface to this SDRAM.

The datasheet TMS320DM6437.pdf states in table 6-16 on page 195 that the maximum frequency of PLL2_SYSCLK1 is 333 MHz. PLL2_SYSCLK1 is the output of PLL2 and is connected internally to the PHY input of DDR2. Because the DDR2 controller divides this by 2, the actual clock supplied to the SDRAM is 166.5 MHz.

I ask this because my SDRAM is capable of much higher frequencies.

Is the the maximum frequency of PLL2_SYSCLK1 really 333 MHz? If not, what is the maximum frequency?

Thanks,

Tim

PS Document SPRU986B (TMS320DM643x DMP DDR Memory Controller) doesn't mention this frequency restriction. I'm currently providing a input of 864 MHz to the DDR2 controller, but it's not working.

Also, this same document states that the DDR2 controller supports DDR2-400. I'm still a little confused about DDR2-400. Does this mean that DDR2-400 SDRAM can be clocked at 400 MHz? Or can it only be clocked at 200 MHz?

over 14 years ago

0 Varada Bellary over 14 years ago

TI__Expert 5750 points

The silicon design team has confirmed that 333MHz is the maximum frequency tested and supported.

Thanks for bringing our attention to the discrepancy in the SPRU986b/c document. It will be reviewed and corrected.

Thanks

Varada

0 Timothy Murtaugh over 14 years ago in reply to Varada Bellary

Expert 1475 points

Varada,

Thanks for the clarification.

I have one more question, it is a general question about DDR2 SDRAM, since this is the first time I've programmed the DDR2 interface.

What is the maximum clock frequency for DDR2-800 SDRAM? I think the maximum clock frequency of the clock signal from the DDR2 controller to the SDRAM is 400 MHz, but because two chucks of data are transferred per clock cycle, the effective data rate is 800 MHz.

Can some tell me if this is true?

Thanks,

Tim

0 Varada Bellary over 14 years ago in reply to Timothy Murtaugh

TI__Expert 5750 points

Yes, because the data is transfered at both riing and falling edge of the clock.

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What is maximum frequency of input to DDR2 controller on TMS320DM6437 processor?