• State Resolved
  • Locked Locked
  • Replies 17 replies
  • Subscribers 97 subscribers
  • Views 1539 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

TDA4VM: TDA4EVM

Arunshankar Dhandayuthapany
Prodigy 160 points
Part Number: TDA4VM


vx_app_signle_cam. out is failing because it is looking for img_test.rw which is not provided in the test data in RTOS downloads

Camera is connected in port 4 of the Fusion board and the initialization is fine

Please find the below logs

root@j7-evm:/opt/vision_apps# ./vx_app_single_cam.out
APP: Init ... !!!
MEM: Init ... !!!
MEM: Initialized DMA HEAP (fd=4) !!!
MEM: Init ... Done !!!
IPC: Init ... !!!
IPC: Init ... Done !!!
REMOTE_SERVICE: Init ... !!!
REMOTE_SERVICE: Init ... Done !!!
104.315179 s: GTC Frequency = 200 MHz
APP: Init ... Done !!!
104.317257 s: VX_ZONE_INIT:Enabled
104.317279 s: VX_ZONE_ERROR:Enabled
104.317285 s: VX_ZONE_WARNING:Enabled
104.319829 s: VX_ZONE_INIT:[tivxInit:71] Initialization Done !!!
104.320023 s: VX_ZONE_INIT:[tivxHostInit:48] Initialization Done for HOST !!

Single Camera Demo - (c) Texas Instruments 2019
========================================================

Usage,
./vx_app_single_cam.out --cfg <config file>

Defaulting to interactive mode
IttCtrl_registerHandler: command echo registered at location 0
IttCtrl_registerHandler: command iss_read_2a_params registered at location 1
IttCtrl_registerHandler: command iss_write_2a_params registered at location 2
IttCtrl_registerHandler: command iss_raw_save registered at location 3
IttCtrl_registerHandler: command iss_yuv_save registered at location 4
IttCtrl_registerHandler: command iss_read_sensor_reg registered at location 5
IttCtrl_registerHandler: command iss_write_sensor_reg registered at location 6
IttCtrl_registerHandler: command dev_ctrl registered at location 7
IttCtrl_registerHandler: command iss_send_dcc_file registered at location 8
NETWORK: Opened at IP Addr = 0.0.0.0, socket port=5000!!!
104.321783 s: ISS: Enumerating sensors ... !!!
104.721504 s: ISS: Enumerating sensors ... found 0 : IMX390-UB953_D3
104.721546 s: ISS: Enumerating sensors ... found 1 : AR0233-UB953_MARS
104.721551 s: ISS: Enumerating sensors ... found 2 : AR0820-UB953_LI
104.721557 s: ISS: Enumerating sensors ... found 3 : UB9xxx_RAW12_TESTPATTERN
104.721562 s: ISS: Enumerating sensors ... found 4 : UB96x_UYVY_TESTPATTERN
104.721567 s: ISS: Enumerating sensors ... found 5 : GW_AR0233_UYVY
Select camera port index 0-7 : 4
0x6 registered sensor drivers
a : IMX390-UB953_D3
b : AR0233-UB953_MARS
c : AR0820-UB953_LI
d : UB9xxx_RAW12_TESTPATTERN
e : UB96x_UYVY_TESTPATTERN
f : GW_AR0233_UYVY
Select a sensor above or press '0' to autodetect the sensor : Invalid selection
. Try again
0x6 registered sensor drivers
a : IMX390-UB953_D3
b : AR0233-UB953_MARS
c : AR0820-UB953_LI
d : UB9xxx_RAW12_TESTPATTERN
e : UB96x_UYVY_TESTPATTERN
f : GW_AR0233_UYVY
Select a sensor above or press '0' to autodetect the sensor : b
Sensor selected : AR0233-UB953_MARS
LDC Selection Yes(1)/No(0) : LDC Selection Yes(1)/No(0) : 1
Querying AR0233-UB953_MARS
113.037830 s: ISS: Querying sensor [AR0233-UB953_MARS] ... !!!
113.037968 s: ISS: Querying sensor [AR0233-UB953_MARS] ... Done !!!
113.037976 s: ISS: Initializing sensor [AR0233-UB953_MARS], doing IM_SENSOR_!
113.038055 s: ISS: Initializing sensor [AR0233-UB953_MARS], doing IM_SENSOR_!
115.636248 s: ISS: Initializing sensor [AR0233-UB953_MARS] ... Done !!!
read_test_image_raw : Unable to open file /opt/vision_apps/test_data/img_test.rw
app_create_viss : sensor_dcc_id = 233
Enabling LDC
Creating LDC
Scaler is enabled


==========================
Demo : Single Camera w/ 2A
==========================

p: Print performance statistics

s: Save Sensor RAW, VISS Output and H3A output images to File System

e: Export performance statistics

u: Update DCC from File System


x: Exit

Enter Choice:
Unsupported command



==========================
Demo : Single Camera w/ 2A
==========================

p: Print performance statistics

s: Save Sensor RAW, VISS Output and H3A output images to File System

e: Export performance statistics

u: Update DCC from File System


x: Exit

Enter Choice: 115.689113 s: ISS: Starting sensor [AR0233-UB953_MARS] ... !!!
116.227333 s: ISS: Starting sensor [AR0233-UB953_MARS] ... !!!
get_dcc_dir_size : Could not open directory or directory is empty /opt/vision_a
[ 129.742470] Initializing XFRM netlink socket
[ 132.522359] process 'docker/tmp/qemu-check041114531/check' started with execk

  • 0
    TI__Guru**** 487215 points

    Hi,

    Even if the test data is not available, usecase will run fine. I see one more error. It seems that DCC binary is not copied, can you please check it?

    get_dcc_dir_size : Could not open directory or directory is empty /opt/vision_a

    Regards,

    Brijesh

  • 0 in reply to Brijesh Jadav
    Prodigy 160 points

    I am following the below steps 1 to 3. And it is not adding this into SD card

    software-dl.ti.com/.../RUN_INSTRUCTIONS.html

    get_dcc_dir_size : Could not open directory or directory is empty /opt/vision_apps/dcc/AR0233-UB953_MARS/wdr

  • 0 in reply to Arunshankar Dhandayuthapany
    TI__Guru**** 487215 points

    Hi Arunshankar,

    This error is also ok to ignore. It just mean there is no dcc profile available in the Linux filesystem, so usecase will run with the default DCC profile available in the imaging folder.

    Can you press 'p' on the console and share the log? 

    This will show if usecase is running fine and it is able to capture and to display the image.

    Regards,

    Brijesh

  • 0 in reply to Brijesh Jadav
    Prodigy 160 points

    I have added dcc from imaging folder into the target and it is not throwing error but not progressing for initialization


    root@j7-evm:/opt/vision_apps# ./vx_app_single_cam.out
    APP: Init ... !!!
    MEM: Init ... !!!
    MEM: Initialized DMA HEAP (fd=4) !!!
    MEM: Init ... Done !!!
    IPC: Init ... !!!
    IPC: Init ... Done !!!
    REMOTE_SERVICE: Init ... !!!
    REMOTE_SERVICE: Init ... Done !!!
    4080.941347 s: GTC Frequency = 200 MHz
    APP: Init ... Done !!!
    4080.943352 s: VX_ZONE_INIT:Enabled
    4080.943372 s: VX_ZONE_ERROR:Enabled
    4080.943378 s: VX_ZONE_WARNING:Enabled
    4080.945682 s: VX_ZONE_INIT:[tivxInit:71] Initialization Done !!!
    4080.945844 s: VX_ZONE_INIT:[tivxHostInit:48] Initialization Done for HOST !!

    Single Camera Demo - (c) Texas Instruments 2019
    ========================================================

    Usage,
    ./vx_app_single_cam.out --cfg <config file>

    Defaulting to interactive mode
    IttCtrl_registerHandler: command echo registered at location 0
    IttCtrl_registerHandler: command iss_read_2a_params registered at location 1
    IttCtrl_registerHandler: command iss_write_2a_params registered at location 2
    IttCtrl_registerHandler: command iss_raw_save registered at location 3
    IttCtrl_registerHandler: command iss_yuv_save registered at location 4
    IttCtrl_registerHandler: command iss_read_sensor_reg registered at location 5
    IttCtrl_registerHandler: command iss_write_sensor_reg registered at location 6
    IttCtrl_registerHandler: command dev_ctrl registered at location 7
    IttCtrl_registerHandler: command iss_send_dcc_file registered at location 8
    NETWORK: Opened at IP Addr = 0.0.0.0, socket port=5000!!!
    4080.947491 s: ISS: Enumerating sensors ... !!!
    4081.347883 s: ISS: Enumerating sensors ... found 0 : IMX390-UB953_D3
    4081.347928 s: ISS: Enumerating sensors ... found 1 : AR0233-UB953_MARS
    4081.347933 s: ISS: Enumerating sensors ... found 2 : AR0820-UB953_LI
    4081.347938 s: ISS: Enumerating sensors ... found 3 : UB9xxx_RAW12_TESTPATTERN
    4081.347944 s: ISS: Enumerating sensors ... found 4 : UB96x_UYVY_TESTPATTERN
    4081.347949 s: ISS: Enumerating sensors ... found 5 : GW_AR0233_UYVY
    Select camera port index 0-7 : 4
    0x6 registered sensor drivers
    a : IMX390-UB953_D3
    b : AR0233-UB953_MARS
    c : AR0820-UB953_LI
    d : UB9xxx_RAW12_TESTPATTERN
    e : UB96x_UYVY_TESTPATTERN
    f : GW_AR0233_UYVY
    Select a sensor above or press '0' to autodetect the sensor : Invalid selection
    . Try again
    0x6 registered sensor drivers
    a : IMX390-UB953_D3
    b : AR0233-UB953_MARS
    c : AR0820-UB953_LI
    d : UB9xxx_RAW12_TESTPATTERN
    e : UB96x_UYVY_TESTPATTERN
    f : GW_AR0233_UYVY
    Select a sensor above or press '0' to autodetect the sensor : b
    Sensor selected : AR0233-UB953_MARS
    LDC Selection Yes(1)/No(0) : LDC Selection Yes(1)/No(0) : 1
    Querying AR0233-UB953_MARS
    4096.525907 s: ISS: Querying sensor [AR0233-UB953_MARS] ... !!!
    4096.526044 s: ISS: Querying sensor [AR0233-UB953_MARS] ... Done !!!
    4096.526052 s: ISS: Initializing sensor [AR0233-UB953_MARS], doing IM_SENSOR_!
    4096.526158 s: ISS: Initializing sensor [AR0233-UB953_MARS], doing IM_SENSOR_!
    4099.122625 s: ISS: Initializing sensor [AR0233-UB953_MARS] ... Done !!!
    read_test_image_raw : Unable to open file /opt/vision_apps/test_data/img_test.rw
    app_create_viss : sensor_dcc_id = 233
    Enabling LDC
    Creating LDC
    Scaler is enabled


    ==========================
    Demo : Single Camera w/ 2A
    ==========================

    p: Print performance statistics

    s: Save Sensor RAW, VISS Output and H3A output images to File System

    e: Export performance statistics

    u: Update DCC from File System


    x: Exit

    Enter Choice:
    Unsupported command



    ==========================
    Demo : Single Camera w/ 2A
    ==========================

    p: Print performance statistics

    s: Save Sensor RAW, VISS Output and H3A output images to File System

    e: Export performance statistics

    u: Update DCC from File System


    x: Exit

    Enter Choice: 4099.169947 s: ISS: Starting sensor [AR0233-UB953_MARS] ... !!!
    4099.707716 s: ISS: Starting sensor [AR0233-UB953_MARS] ... !!!
    p


    Summary of CPU load,
    ====================

    CPU: mpu1_0: TOTAL LOAD = 0.32 % ( HWI = 0. 3 %, SWI = 0. 0 % )
    CPU: mcu2_0: TOTAL LOAD = 61. 0 % ( HWI = 0. 0 %, SWI = 0. 0 % )
    CPU: mcu2_1: TOTAL LOAD = 42925856.96 % ( HWI = 0. 0 %, SWI = 0. 0 % )
    CPU: c6x_1: TOTAL LOAD = 0. 5 % ( HWI = 0. 2 %, SWI = 0. 1 % )
    CPU: c6x_2: TOTAL LOAD = 0. 5 % ( HWI = 0. 2 %, SWI = 0. 1 % )
    CPU: c7x_1: TOTAL LOAD = 0. 7 % ( HWI = 0. 3 %, SWI = 0. 2 % )


    HWA performance statistics,
    ===========================

    HWA: VISS: LOAD = 0.12 % ( 0 MP/s )
    HWA: LDC : LOAD = 0. 9 % ( 0 MP/s )
    HWA: MSC0: LOAD = 0.14 % ( 0 MP/s )


    DDR performance statistics,
    ===========================

    DDR: READ BW: AVG = 0 MB/s, PEAK = 0 MB/s
    DDR: WRITE BW: AVG = 0 MB/s, PEAK = 0 MB/s
    DDR: TOTAL BW: AVG = 0 MB/s, PEAK = 0 MB/s


    Detailed CPU performance/memory statistics,
    ===========================================

    CPU: mcu2_0: TASK: IPC_RX: 1. 2 %
    CPU: mcu2_0: TASK: REMOTE_SRV: 13.83 %
    CPU: mcu2_0: TASK: LOAD_TEST: 0. 0 %
    CPU: mcu2_0: TASK: TIVX_CPU: 45.26 %
    CPU: mcu2_0: TASK: TIVX_NF: 0. 0 %
    CPU: mcu2_0: TASK: TIVX_LDC1: 5.76 %
    CPU: mcu2_0: TASK: TIVX_MSC1: 0. 0 %
    CPU: mcu2_0: TASK: TIVX_MSC2: 0. 0 %
    CPU: mcu2_0: TASK: TIVX_VISS1: 7.11 %
    CPU: mcu2_0: TASK: TIVX_CAPT1: 0. 0 %
    CPU: mcu2_0: TASK: TIVX_CAPT2: 0. 0 %
    CPU: mcu2_0: TASK: TIVX_DISP1: 0. 0 %
    CPU: mcu2_0: TASK: TIVX_DISP2: 0. 0 %
    CPU: mcu2_0: TASK: TIVX_CSITX: 0. 0 %
    CPU: mcu2_0: TASK: TIVX_CAPT3: 0. 0 %
    CPU: mcu2_0: TASK: TIVX_CAPT4: 0. 0 %

    CPU: mcu2_0: HEAP: DDR_SHARED_MEM: size = 16777216 B, free = 16262656 B ()
    CPU: mcu2_0: HEAP: L3_MEM: size = 262144 B, free = 261888 B ()
    CPU: mcu2_0: HEAP: DDR_NON_CACHE_M: size = 16777216 B, free = 16776960 B ()

    CPU: mcu2_1: TASK: IPC_RX: 0. 0 %
    CPU: mcu2_1: TASK: REMOTE_SRV: 4.95 %
    CPU: mcu2_1: TASK: LOAD_TEST: 0. 0 %
    CPU: mcu2_1: TASK: TIVX_SDE: 0. 0 %
    CPU: mcu2_1: TASK: TIVX_DOF: 0. 0 %
    CPU: mcu2_1: TASK: IPC_TEST_RX: 0. 0 %
    CPU: mcu2_1: TASK: IPC_TEST_TX: 0. 0 %
    CPU: mcu2_1: TASK: IPC_TEST_TX: 0. 0 %
    CPU: mcu2_1: TASK: IPC_TEST_TX: 0. 0 %
    CPU: mcu2_1: TASK: IPC_TEST_TX: 0. 0 %
    CPU: mcu2_1: TASK: IPC_TEST_TX: 0. 0 %

    CPU: mcu2_1: HEAP: DDR_SHARED_MEM: size = 16777216 B, free = 16773376 B ()
    CPU: mcu2_1: HEAP: L3_MEM: size = 262144 B, free = 262144 B ()
    CPU: mcu2_1: HEAP: DDR_NON_CACHE_M: size = 117440512 B, free = 117440256 B ()

    CPU: c6x_1: TASK: IPC_RX: 0. 0 %
    CPU: c6x_1: TASK: REMOTE_SRV: 0. 0 %
    CPU: c6x_1: TASK: LOAD_TEST: 0. 0 %
    CPU: c6x_1: TASK: TIVX_CPU: 0. 0 %
    CPU: c6x_1: TASK: IPC_TEST_RX: 0. 0 %
    CPU: c6x_1: TASK: IPC_TEST_TX: 0. 0 %
    CPU: c6x_1: TASK: IPC_TEST_TX: 0. 0 %
    CPU: c6x_1: TASK: IPC_TEST_TX: 0. 0 %
    CPU: c6x_1: TASK: IPC_TEST_TX: 0. 0 %
    CPU: c6x_1: TASK: IPC_TEST_TX: 0. 0 %

    CPU: c6x_1: HEAP: DDR_SHARED_MEM: size = 16777216 B, free = 16774912 B ()
    CPU: c6x_1: HEAP: L2_MEM: size = 229376 B, free = 229376 B ()
    CPU: c6x_1: HEAP: DDR_SCRATCH_MEM: size = 50331648 B, free = 50331648 B ()

    CPU: c6x_2: TASK: IPC_RX: 0. 0 %
    CPU: c6x_2: TASK: REMOTE_SRV: 0. 0 %
    CPU: c6x_2: TASK: LOAD_TEST: 0. 0 %
    CPU: c6x_2: TASK: TIVX_CPU: 0. 0 %
    CPU: c6x_2: TASK: IPC_TEST_RX: 0. 0 %
    CPU: c6x_2: TASK: IPC_TEST_TX: 0. 0 %
    CPU: c6x_2: TASK: IPC_TEST_TX: 0. 0 %
    CPU: c6x_2: TASK: IPC_TEST_TX: 0. 0 %
    CPU: c6x_2: TASK: IPC_TEST_TX: 0. 0 %
    CPU: c6x_2: TASK: IPC_TEST_TX: 0. 0 %

    CPU: c6x_2: HEAP: DDR_SHARED_MEM: size = 16777216 B, free = 16774912 B ()
    CPU: c6x_2: HEAP: L2_MEM: size = 229376 B, free = 229376 B ()
    CPU: c6x_2: HEAP: DDR_SCRATCH_MEM: size = 50331648 B, free = 50331648 B ()

    CPU: c7x_1: TASK: IPC_RX: 0. 0 %
    CPU: c7x_1: TASK: REMOTE_SRV: 0. 0 %
    CPU: c7x_1: TASK: LOAD_TEST: 0. 0 %
    CPU: c7x_1: TASK: TIVX_CPU: 0. 0 %
    CPU: c7x_1: TASK: IPC_TEST_RX: 0. 0 %
    CPU: c7x_1: TASK: IPC_TEST_TX: 0. 0 %
    CPU: c7x_1: TASK: IPC_TEST_TX: 0. 0 %
    CPU: c7x_1: TASK: IPC_TEST_TX: 0. 0 %
    CPU: c7x_1: TASK: IPC_TEST_TX: 0. 0 %
    CPU: c7x_1: TASK: IPC_TEST_TX: 0. 0 %

    CPU: c7x_1: HEAP: DDR_SHARED_MEM: size = 268435456 B, free = 268435456 B ()
    CPU: c7x_1: HEAP: L3_MEM: size = 8159232 B, free = 8159232 B ()
    CPU: c7x_1: HEAP: L2_MEM: size = 491520 B, free = 491520 B ()
    CPU: c7x_1: HEAP: L1_MEM: size = 16384 B, free = 16384 B ()
    CPU: c7x_1: HEAP: DDR_SCRATCH_MEM: size = 268435456 B, free = 268435456 B ()


    GRAPH: graph_84 (#nodes = 6, #executions = 1138)
    NODE: CAPTURE2: node_95: avg = 33809 usecs, min/max = 3368
    NODE: VPAC_VISS1: VISS_Processing: avg = 4576 usecs, min/max = 458
    NODE: IPU1-0: 2A_AlgNode: avg = 2266 usecs, min/max = 218
    NODE: VPAC_LDC1: node_111: avg = 3410 usecs, min/max = 338
    NODE: VPAC_MSC1: node_113: avg = 5149 usecs, min/max = 518
    NODE: DISPLAY1: node_115: avg = 8522 usecs, min/max = 8

    PERF: TOTAL: avg = 33879 usecs, min/max = 33544 / 46741 usecs, #9

    PERF: TOTAL: 29.51 FPS

  • 0 in reply to Arunshankar Dhandayuthapany
    TI__Guru**** 487215 points

    Hi,

    It seems to be running fine. The entire graph is running at almost 30fps, as expected. i dont see any issue.

    Do you see anything on the display? eDP display should come up and display some captured images from camera. Could you please check eDP output?

    Regards,

    Brijesh

  • 0 in reply to Brijesh Jadav
    Prodigy 160 points

    I have connected my monitor to eDP dispaly DISPLAY0 zero port and I do not see any signal getting into it. 

  • 0 in reply to Arunshankar Dhandayuthapany
    TI__Guru**** 487215 points

    Hi,

    Can you share share output of running vision_apps_init.sh script?

    Regards,

    Brijesh

  • 0
    Prodigy 160 points

    oot@j7-evm:/opt/vision_apps# [MCU2_0]  60951.377939 s: CIO: Init ... Done !!!  
    [MCU2_0]  60951.377990 s: ### CPU Frequency = 1000000000 Hz                     
    [MCU2_0]  60951.378021 s: APP: Init ... !!!                                     
    [MCU2_0]  60951.378040 s: SCICLIENT: Init ... !!!                               
    [MCU2_0]  60951.378256 s: SCICLIENT: DMSC FW version [21.5.0--v2021.05 (Terrific
     Llam]                                                                          
    [MCU2_0]  60951.378291 s: SCICLIENT: DMSC FW revision 0x15                      
    [MCU2_0]  60951.378316 s: SCICLIENT: DMSC FW ABI revision 3.1                   
    [MCU2_0]  60951.378341 s: SCICLIENT: Init ... Done !!!                          
    [MCU2_0]  60951.378362 s: UDMA: Init ... !!!                                    
    [MCU2_0]  60951.379339 s: UDMA: Init ... Done !!!                               
    [MCU2_0]  60951.379387 s: MEM: Init ... !!!                                     
    [MCU2_0]  60951.379418 s: MEM: Created heap (DDR_SHARED_MEM, id=0, flags=0x00000
    004) @ e1000000 of size 16777216 bytes !!!                                      
    [MCU2_0]  60951.379471 s: MEM: Created heap (L3_MEM, id=1, flags=0x00000000) @ 3
    600000 of size 262144 bytes !!!                                                 
    [MCU2_0]  60951.379516 s: MEM: Created heap (DDR_NON_CACHE_ME, id=5, flags=0x000
    00000) @ d8000000 of size 16777216 bytes !!!                                    
    [MCU2_0]  60951.379560 s: MEM: Init ... Done !!!                                
    [MCU2_0]  60951.379579 s: IPC: Init ... !!!                                     
    [MCU2_0]  60951.379623 s: IPC: 6 CPUs participating in IPC !!!                  
    [MCU2_0]  60951.379662 s: IPC: Waiting for HLOS to be ready ... !!!             
    [MCU2_0]  60966.059048 s: IPC: HLOS is ready !!!                                
    [MCU2_0]  60966.064256 s: IPC: Init ... Done !!!                                
    [MCU2_0]  60966.064312 s: APP: Syncing with 5 CPUs ... !!!                      
    [MCU2_0]  60966.994385 s: APP: Syncing with 5 CPUs ... Done !!!                 
    [MCU2_0]  60966.994427 s: REMOTE_SERVICE: Init ... !!!                          
    [MCU2_0]  60966.995746 s: REMOTE_SERVICE: Init ... Done !!!                     
    [MCU2_0]  60966.995846 s: ETHFW: Init ... !!!                                   
    [MCU2_0]  60967.014229 s: CPSW_9G Test on MAIN NAVSS                            
    [MCU2_0]  60967.027707 s: ETHFW: Version   : 0.01.01                            
    [MCU2_0]  60967.027763 s: ETHFW: Build Date: Aug 12, 2021                       
    [MCU2_0]  60967.027792 s: ETHFW: Build Time: 11:51:44                           
    [MCU2_0]  60967.027816 s: ETHFW: Commit SHA: fc8c791d                           
    [MCU2_0]  60967.027870 s: ETHFW: Init ... DONE !!!                              
    [MCU2_0]  60967.027898 s: ETHFW: Remove server Init ... !!!                     
    [MCU2_0]  60967.028637 s: Remote demo device (core : mcu2_0) .....              
    [MCU2_0]  60967.028698 s: ETHFW: Remove server Init ... DONE !!!                
    [MCU2_0]  60967.029620 s: Starting lwIP, local interface IP is dhcp-enabled     
    [MCU2_0]  60967.035305 s: Host MAC address: 70:ff:76:1d:92:c2                   
    [MCU2_0]  60967.078689 s: FVID2: Init ... !!!                                   
    [MCU2_0]  60967.078792 s: FVID2: Init ... Done !!!                              
    [MCU2_0]  60967.078834 s: DSS: Init ... !!!                                     
    [MCU2_0]  60967.078859 s: DSS: Display type is eDP !!!                          
    [MCU2_0]  60967.078883 s: DSS: M2M Path is enabled !!!                          
    [MCU2_0]  60967.078903 s: DSS: SoC init ... !!!                                 
    [MCU2_0]  60967.078924 s: SCICLIENT: Sciclient_pmSetModuleState module=152 state
    =2                                                                              
    [MCU2_0]  60967.079100 s: SCICLIENT: Sciclient_pmSetModuleState success         
    [MCU2_0]  60967.079132 s: SCICLIENT: Sciclient_pmSetModuleState module=297 state
    =2                                                                              
    [MCU2_0]  60967.079280 s: SCICLIENT: Sciclient_pmSetModuleState success         
    [MCU2_0]  60967.079308 s: SCICLIENT: Sciclient_pmSetModuleState module=151 state
    =2                                                                              
    [MCU2_0]  60967.079425 s: SCICLIENT: Sciclient_pmSetModuleState success         
    [MCU2_0]  60967.079452 s: SCICLIENT: Sciclient_pmSetModuleClkParent module=152 c
    lk=9 parent=11                                                                  
    [MCU2_0]  60967.079533 s: SCICLIENT: Sciclient_pmSetModuleClkParent success     
    [MCU2_0]  60967.079563 s: SCICLIENT: Sciclient_pmSetModuleClkParent module=152 c
    lk=13 parent=18                                                                 
    [MCU2_0]  60967.079638 s: SCICLIENT: Sciclient_pmSetModuleClkParent success     
    [MCU2_0]  60967.079754 s: SCICLIENT: Sciclient_pmSetModuleClkParent module=152 c
    lk=1 parent=2                                                                   
    [MCU2_0]  60967.079858 s: SCICLIENT: Sciclient_pmSetModuleClkParent success     
    [MCU2_0]  60967.079888 s: SCICLIENT: Sciclient_pmSetModuleClkFreq module=152 clk
    =1 freq=148500000                                                               
    [MCU2_0]  60967.080879 s: SCICLIENT: Sciclient_pmSetModuleClkFreq success       
    [MCU2_0]  60967.080918 s: SCICLIENT: Sciclient_pmModuleClkRequest module=152 clk
    =1 state=2 flag=0                                                               
    [MCU2_0]  60967.081057 s: SCICLIENT: Sciclient_pmModuleClkRequest success       
    [MCU2_0]  60967.081089 s: DSS: SoC init ... Done !!!                            
    [MCU2_0]  60967.081112 s: DSS: Board init ... !!!                               
    [MCU2_0]  60967.081132 s: DSS: Board init ... Done !!!                          
    [MCU2_0]  60967.105551 s: DSS: Init ... Done !!!                                
    [MCU2_0]  60967.105605 s: VHWA: VPAC Init ... !!!                               
    [MCU2_0]  60967.105629 s: SCICLIENT: Sciclient_pmSetModuleState module=290 state
    =2                                                                              
    [MCU2_0]  60967.105879 s: SCICLIENT: Sciclient_pmSetModuleState success         
    [MCU2_0]  60967.105917 s: VHWA: LDC Init ... !!!                                
    [MCU2_0]  60967.109087 s: VHWA: LDC Init ... Done !!!                           
    [MCU2_0]  60967.109135 s: VHWA: MSC Init ... !!!                                
    [MCU2_0]  60967.118460 s: VHWA: MSC Init ... Done !!!                           
    [MCU2_0]  60967.118506 s: VHWA: NF Init ... !!!                                 
    [MCU2_0]  60967.120169 s: VHWA: NF Init ... Done !!!                            
    [MCU2_0]  60967.120213 s: VHWA: VISS Init ... !!!                               
    [MCU2_0]  60967.130156 s: VHWA: VISS Init ... Done !!!                          
    [MCU2_0]  60967.130207 s: VHWA: VPAC Init ... Done !!!                          
    [MCU2_0]  60967.130246 s:  VX_ZONE_INIT:Enabled                                 
    [MCU2_0]  60967.130276 s:  VX_ZONE_ERROR:Enabled                                
    [MCU2_0]  60967.130300 s:  VX_ZONE_WARNING:Enabled                              
    [MCU2_0]  60967.131313 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:55] Added ta
    rget IPU1-0                                                                     
    [MCU2_0]  60967.131497 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:55] Added ta
    rget VPAC_NF                                                                    
    [MCU2_0]  60967.131800 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:55] Added ta
    rget VPAC_LDC1                                                                  
    [MCU2_0]  60967.132011 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:55] Added ta
    rget VPAC_MSC1                                                                  
    [MCU2_0]  60967.132210 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:55] Added ta
    rget VPAC_MSC2                                                                  
    [MCU2_0]  60967.132452 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:55] Added ta
    rget VPAC_VISS1                                                                 
    [MCU2_0]  60967.132782 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:55] Added ta
    rget CAPTURE1                                                                   
    [MCU2_0]  60967.133014 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:55] Added ta
    rget CAPTURE2                                                                   
    [MCU2_0]  60967.133227 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:55] Added ta
    rget DISPLAY1                                                                   
    [MCU2_0]  60967.133442 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:55] Added ta
    rget DISPLAY2                                                                   
    [MCU2_0]  60967.133623 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:55] Added ta
    rget CSITX                                                                      
    [MCU2_0]  60967.133945 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:55] Added ta
    rget CAPTURE3                                                                   
    [MCU2_0]  60967.134171 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:55] Added ta
    rget CAPTURE4                                                                   
    [MCU2_0]  60967.134396 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:55] Added ta
    rget CAPTURE5                                                                   
    [MCU2_0]  60967.134615 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:55] Added ta
    rget CAPTURE6                                                                   
    [MCU2_0]  60967.134926 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:55] Added ta
    rget CAPTURE7                                                                   
    [MCU2_0]  60967.135165 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:55] Added ta
    rget CAPTURE8                                                                   
    [MCU2_0]  60967.135361 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:55] Added ta
    rget DSS_M2M1                                                                   
    [MCU2_0]  60967.135555 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:55] Added ta
    rget DSS_M2M2                                                                   
    [MCU2_0]  60967.135872 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:55] Added ta
    rget DSS_M2M3                                                                   
    [MCU2_0]  60967.136093 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:55] Added ta
    rget DSS_M2M4                                                                   
    [MCU2_0]  60967.136145 s:  VX_ZONE_INIT:[tivxInit:71] Initialization Done !!!   
    [MCU2_0]  60967.136173 s: APP: OpenVX Target kernel init ... !!!                
    [MCU2_0]  60967.148646 s: APP: OpenVX Target kernel init ... Done !!!           
    [MCU2_0]  60967.148786 s: CSI2RX: Init ... !!!                                  
    [MCU2_0]  60967.148811 s: SCICLIENT: Sciclient_pmSetModuleState module=25 state=
    2                                                                               
    [MCU2_0]  60967.148916 s: SCICLIENT: Sciclient_pmSetModuleState success         
    [MCU2_0]  60967.148947 s: SCICLIENT: Sciclient_pmSetModuleState module=26 state=
    2                                                                               
    [MCU2_0]  60967.149049 s: SCICLIENT: Sciclient_pmSetModuleState success         
    [MCU2_0]  60967.149075 s: SCICLIENT: Sciclient_pmSetModuleState module=27 state=
    2                                                                               
    [MCU2_0]  60967.149160 s: SCICLIENT: Sciclient_pmSetModuleState success         
    [MCU2_0]  60967.149185 s: SCICLIENT: Sciclient_pm67.157150 s: IPC: Echo status:
    mpu1_0[x] mcu2_0[s] mcu2_1[.] C66X_1[P] C66X_2[P] C7X_1[P]                      
    [MCU2_0]  60967.157219 s: IPC: Echo status: mpu1_0[x] mcu2_0[s] mcu2_1[P] C66X_1
    [P] C66X_2[P] C7X_1[P]                                                          
    [MCU2_0]  60967.158745 s: [LWIPIF_LWIP] NETIF INIT SUCCESS                      
    [MCU2_0]  60967.158802 s: Added interface 'ti1', IP is 0.0.0.0                  
    [MCU2_0]  60969.585903 s: Function:CpswProxyServer_registerMacHandlerCb,HostId:0
    ,Handle:a2fb6054,CoreKey:38acb7e6, MacAddress:70:ff:76:1d:92:c1, FlowIdx:172, Fl
    owIdxOffset:0                                                                   
    [MCU2_0]  60969.589003 s: Cpsw_ioctlInternal: CPSW: Registered MAC address.ALE e
    ntry:12, Policer Entry:1                                                        
    [MCU2_1]  60951.368789 s: CIO: Init ... Done !!!                                
    [MCU2_1]  60951.368845 s: ### CPU Frequency = 1000000000 Hz                     
    [MCU2_1]  60951.368876 s: APP: Init ... !!!                                     
    [MCU2_1]  60951.368895 s: SCICLIENT: Init ... !!!                               
    [MCU2_1]  60951.369107 s: SCICLIENT: DMSC FW version [21.5.0--v2021.05 (Terrific
     Llam]                                                                          
    [MCU2_1]  60951.369142 s: SCICLIENT: DMSC FW revision 0x15                      
    [MCU2_1]  60951.369167 s: SCICLIENT: DMSC FW ABI revision 3.1                   
    [MCU2_1]  60951.369191 s: SCICLIENT: Init ... Done !!!                          
    [MCU2_1]  60951.369212 s: UDMA: Init ... !!!                                    
    [MCU2_1]  60951.370330 s: UDMA: Init ... Done !!!                               
    [MCU2_1]  60951.370375 s: MEM: Init ... !!!                                     
    [MCU2_1]  60951.370417 s: MEM: Created heap (DDR_SHARED_MEM, id=0, flags=0x00000
    004) @ e2000000 of size 16777216 bytes !!!                                      
    [MCU2_1]  60951.370472 s: MEM: Created heap (L3_MEM, id=1, flags=0x00000001) @ 3
    640000 of size 262144 bytes !!!                                                 
    [MCU2_1]  60951.370516 s: MEM: Created heap (DDR_NON_CACHE_ME, id=5, flags=0x000
    00000) @ d9000000 of size 117440512 bytes !!!                                   
    [MCU2_1]  60951.370560 s: MEM: Init ... Done !!!                                
    [MCU2_1]  60951.370580 s: IPC: Init ... !!!                                     
    [MCU2_1]  60951.370626 s: IPC: 6 CPUs participating in IPC !!!                  
    [MCU2_1]  60951.370663 s: IPC: Waiting for HLOS to be ready ... !!!             
    [MCU2_1]  60966.989336 s: IPC: HLOS is ready !!!                                
    [MCU2_1]  60966.994299 s: IPC: Init ... Done !!!                                
    [MCU2_1]  60966.994346 s: APP: Syncing with 5 CPUs ... !!!                      
    [MCU2_1]  60966.994384 s: APP: Syncing with 5 CPUs ... Done !!!                 
    [MCU2_1]  60966.994420 s: REMOTE_SERVICE: Init ... !!!                          
    [MCU2_1]  60966.995726 s: REMOTE_SERVICE: Init ... Done !!!                     
    [MCU2_1]  60966.995817 s: FVID2: Init ... !!!                                   
    [MCU2_1]  60966.995880 s: FVID2: Init ... Done !!!                              
    [MCU2_1]  60966.995910 s: VHWA: DMPAC: Init ... !!!                             
    [MCU2_1]  60966.995932 s: SCICLIENT: Sciclient_pmSetModuleState module=48 state=
    2                                                                               
    [MCU2_1]  60966.996076 s: SCICLIENT: Sciclient_pmSetModuleState success         
    [MCU2_1]  60966.996106 s: SCICLIENT: Sciclient_pmSetModuleState module=305 state
    =2                                                                              
    [MCU2_1]  60966.996204 s: SCICLIENT: Sciclient_pmSetModuleState success         
    [MCU2_1]  60966.996233 s: VHWA: DOF Init ... !!!                                
    [MCU2_1]  60967.004050 s: VHWA: DOF Init ... Done !!!                           
    [MCU2_1]  60967.004099 s: VHWA: SDE Init ... !!!                                
    [MCU2_1]  60967.006344 s: VHWA: SDE Init ... Done !!!                           
    [MCU2_1]  60967.006396 s: VHWA: DMPAC: Init ... Done !!!                        
    [MCU2_1]  60967.006438 s:  VX_ZONE_INIT:Enabled                                 
    [MCU2_1]  60967.006465 s:  VX_ZONE_ERROR:Enabled                                
    [MCU2_1]  60967.006489 s:  VX_ZONE_WARNING:Enabled                              
    [MCU2_1]  60967.007373 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:55] Added ta
    rget DMPAC_SDE                                                                  
    [MCU2_1]  60967.007567 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:55] Added ta
    rget DMPAC_DOF                                                                  
    [MCU2_1]  60967.007626 s:  VX_ZONE_INIT:[tivxInit:71] Initialization Done !!!   
    [MCU2_1]  60967.007658 s: APP: OpenVX Target kernel init ... !!!                
    [MCU2_1]  60967.007872 s: APP: OpenVX Target kernel init ... Done !!!           
    [MCU2_1]  60967.007909 s: UDMA Copy: Init ... !!!                               
    [MCU2_1]  60967.009427 s: UDMA Copy: Init ... Done !!!                          
    [MCU2_1]  60967.009480 s: APP: Init ... Done !!!                                
    [MCU2_1]  60967.009508 s: APP: Run ... !!!                                      
    [MCU2_1]  60967.009527 s: IPC: Starting echo test ...                           
    [MCU2_1]  60967.011366 s: APP: Run ... Done !!!                                 
    [MCU2_1]  60967.012222 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[s] C66X_1
    [P] C66X_2[.] C7X_1[.]                                                          
    [MCU2_1]  60967.012309 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[s] C66X_1
    [P] C66X_2[P] C7X_1[.]                                                          
    [MCU2_1]  60967.012382 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[s] C66X_1
    [P] C66X_2[P] C7X_1[P]                                                          
    [MCU2_1]  60967.156670 s: IPC: Echo status: mpu1_0[x] mcu2_0[P] mcu2_1[s] C66X_1
    [P] C66X_2[P] C7X_1[P]                                                          
    [C6x_1 ]  60951.452700 s: CIO: Init ... Done !!!                                
    [C6x_1 ]  60951.452725 s: ### CPU Frequency = 1350000000 Hz                     
    [C6x_1 ]  60951.452737 s: APP: Init ... !!!                                     
    [C6x_1 ]  60951.452746 s: SCICLIENT: Init ... !!!                               
    [C6x_1 ]  60951.452939 s: SCICLIENT: DMSC FW version [21.5.0--v2021.05 (Terrific
     Llam]                                                                          
    [C6x_1 ]  60951.452954 s: SCICLIENT: DMSC FW revision 0x15                      
    [C6x_1 ]  60951.452964 s: SCICLIENT: DMSC FW ABI revision 3.1                   
    [C6x_1 ]  60951.452975 s: SCICLIENT: Init ... Done !!!                          
    [C6x_1 ]  60951.452986 s: UDMA: Init ... !!!                                    
    [C6x_1 ]  60951.454172 s: UDMA: Init ... Done !!!                               
    [C6x_1 ]  60951.454195 s: MEM: Init ... !!!                                     
    [C6x_1 ]  60951.454208 s: MEM: Created heap (DDR_SHARED_MEM, id=0, flags=0x00000
    004) @ e4000000 of size 16777216 bytes !!!                                      
    [C6x_1 ]  60951.454226 s: MEM: Created heap (L2_MEM, id=2, flags=0x00000001) @ 8
    00000 of size 229376 bytes !!!                                                  
    [C6x_1 ]  60951.454243 s: MEM: Created heap (DDR_SCRATCH_MEM, id=4, flags=0x0000
    0001) @ e5000000 of size 50331648 bytes !!!                                     
    [C6x_1 ]  60951.454260 s: MEM: Init ... Done !!!                                
    [C6x_1 ]  60951.454269 s: IPC: Init ... !!!                                     
    [C6x_1 ]  60951.454289 s: IPC: 6 CPUs participating in IPC !!!                  
    [C6x_1 ]  60951.454303 s: IPC: Waiting for HLOS to be ready ... !!!             
    [C6x_1 ]  60964.400135 s: IPC: HLOS is ready !!!                                
    [C6x_1 ]  60964.403573 s: IPC: Init ... Done !!!                                
    [C6x_1 ]  60964.403601 s: APP: Syncing with 5 CPUs ... !!!                      
    [C6x_1 ]  60966.994384 s: APP: Syncing with 5 CPUs ... Done !!!                 
    [C6x_1 ]  60966.994400 s: REMOTE_SERVICE: Init ... !!!                          
    [C6x_1 ]  60966.995043 s: REMOTE_SERVICE: Init ... Done !!!                     
    [C6x_1 ]  60966.995081 s:  VX_ZONE_INIT:Enabled                                 
    [C6x_1 ]  60966.995094 s:  VX_ZONE_ERROR:Enabled                                
    [C6x_1 ]  60966.995105 s:  VX_ZONE_WARNING:Enabled                              
    [C6x_1 ]  60966.995958 s:  VX_ZONE_INIT:[tivxInit:71] Initialization Done !!!   
    [C6x_1 ]  60966.995976 s: APP: OpenVX Target kernel init ... !!!                
    [C6x_1 ]  60966.996257 s: APP: OpenVX Target kernel init ... Done !!!           
    [C6x_1 ]  60966.996279 s: UDMA Copy: Init ... !!!                               
    [C6x_1 ]  60966.999534 s: UDMA Copy: Init ... Done !!!                          
    [C6x_1 ]  60966.999554 s: APP: Init ... Done !!!                                
    [C6x_1 ]  60967.000228 s: APP: Run ... !!!                                      
    [C6x_1 ]  60967.000251 s: IPC: Starting echo test ...                           
    [C6x_1 ]  60967.001419 s: APP: Run ... Done !!!                                 
    [C6x_1 ]  60967.001734 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[x] C66X_1
    [s] C66X_2[P] C7X_1[.]                                                          
    [C6x_1 ]  60967.001765 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[x] C66X_1
    [s] C66X_2[P] C7X_1[P]                                                          
    [C6x_1 ]  60967.012045 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[P] C66X_1
    [s] C66X_2[P] C7X_1[P]                                                          
    [C6x_1 ]  60967.156607 s: IPC: Echo status: mpu1_0[x] mcu2_0[P] mcu2_1[P] C66X_1
    [s] C66X_2[P] C7X_1[P]                                                          
    [C6x_2 ]  60951.540468 s: CIO: Init ... Done !!!                                
    [C6x_2 ]  60951.540503 s: ### CPU Frequency = 1350000000 Hz                     
    [C6x_2 ]  60951.540514 s: APP: Init ... !!!                                     
    [C6x_2 ]  60951.540523 s: SCICLIENT: Init ... !!!                               
    [C6x_2 ]  60951.540717 s: SCICLIENT: DMSC FW version [21.5.0--v2021.05 (Terrific
     Llam]                                                                          
    [C6x_2 ]  60951.540731 s: SCICLIENT: DMSC FW revision 0x15                      
    [C6x_2 ]  60951.540741 s: SCICLIENT: DMSC FW ABI revision 3.1                   
    [C6x_2 ]  60951.540752 s: SCICLIENT: Init ... Done !!!                          
    [C6x_2 ]  60951.540761 s: UDMA: Init ... !!!                                    
    [C6x_2 ]  60951.541974 s: UDMA: Init ... Done !!!                               
    [C6x_2 ]  60951.541998 s: MEM: Init ... !!!                                     
    [C6x_2 ]  60951.542010 s: MEM: Created heap (DDR_SHARED_MEM, id=0, flags=0x00000
    004) @ e8000000 of size 16777216 bytes !!!                                      
    [C6x_2 ]  60951.542029 s: MEM: Created heap (L2_MEM, id=2, flags=0x00000001) @ 8
    00000 of size 229376 bytes !!!                                                  
    [C6x_2 ]  60951.542045 s: MEM: Created heap (DDR_SCRATCH_MEM, id=4, flags=0x0000
    0001) @ e9000000 of size 50331648 bytes !!!                                     
    [C6x_2 ]  60951.542062 s: MEM: Init ... Done !!!                                
    [C6x_2 ]  60951.542071 s: IPC: Init ... !!!                                     
    [C6x_2 ]  60951.542090 s: IPC: 6 CPUs participating in IPC !!!                  
    [C6x_2 ]  60951.542104 s: IPC: Waiting for HLOS to be ready ... !!!             
    [C6x_2 ]  60965.611927 s: IPC: HLOS is ready !!!                                
    [C6x_2 ]  60965.615306 s: IPC: Init ... Done !!!                                
    [C6x_2 ]  60965.615334 s: APP: Syncing with 5 CPUs ... !!!                      
    [C6x_2 ]  60966.994384 s: APP: Syncing with 5 CPUs ... Done !!!                 
    [C6x_2 ]  60966.994400 s: REMOTE_SERVICE: Init ... !!!                          
    [C6x_2 ]  60966.995047 s: REMOTE_SERVICE: Init ... Done !!!                     
    [C6x_2 ]  60966.995086 s:  VX_ZONE_INIT:Enabled                                 
    [C6x_2 ]  60966.995097 s:  VX_ZONE_ERROR:Enabled                                
    [C6x_2 ]  60966.995106 s:  VX_ZONE_WARNING:Enabled                              
    [C6x_2 ]  60966.995945 s:  VX_ZONE_INIT:[tivxInit:71] Initialization Done !!!   
    [C6x_2 ]  60966.995962 s: APP: OpenVX Target kernel init ... !!!                
    [C6x_2 ]  60966.996247 s: APP: OpenVX Target kernel init ... Done !!!           
    [C6x_2 ]  60966.996270 s: UDMA Copy: Init ... !!!                               
    [C6x_2 ]  60966.999422 s: UDMA Copy: Init ... Done !!!                          
    [C6x_2 ]  60966.999442 s: APP: Init ... Done !!!                                
    [C6x_2 ]  60967.000127 s: APP: Run ... !!!                                      
    [C6x_2 ]  60967.000138 s: IPC: Starting echo test ...                           
    [C6x_2 ]  60967.001225 s: APP: Run ... Done !!!                                 
    [C6x_2 ]  60967.001518 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[x] C66X_1
    [x] C66X_2[s] C7X_1[P]                                                          
    [C6x_2 ]  60967.001733 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[x] C66X_1
    [P] C66X_2[s] C7X_1[P]                                                          
    [C6x_2 ]  60967.012066 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[P] C66X_1
    [P] C66X_2[s] C7X_1[P]                                                          
    [C6x_2 ]  60967.156618 s: IPC: Echo status: mpu1_0[x] mcu2_0[P] mcu2_1[P] C66X_1
    [P] C66X_2[s] C7X_1[P]                                                          
    [C7x_1 ]  60951.749680 s: CIO: Init ... Done !!!                                
    [C7x_1 ]  60951.749695 s: ### CPU Frequency = 1000000000 Hz                     
    [C7x_1 ]  60951.749706 s: APP: Init ... !!!                                     
    [C7x_1 ]  60951.749714 s: SCICLIENT: Init ... !!!                               
    [C7x_1 ]  60951.749884 s           

  • 0 in reply to Arunshankar Dhandayuthapany
    Prodigy 160 points

    Hi Brijesh,

    I do not see any init issues with DSS. Please let me know how to proceed or any other data you want as this could be resolved in minutes if we have a Skype call.

  • 0 in reply to Brijesh Jadav
    Prodigy 160 points

    Even after applying the patch there is no change

  • 0 in reply to Brijesh Jadav
    Prodigy 160 points

    Even after applying the patch there is no change

  • 0 in reply to Arunshankar Dhandayuthapany
    TI__Guru**** 487215 points

    Hi Arunshankar,

    Does your display support 1080p resolution? Could you please confirm that you are using eDP display?

    Regards,

    Brijesh

  • 0 in reply to Brijesh Jadav
    Prodigy 160 points

    Yes it supports 1080p and I am using eDP DISPLAY0

  • +1 in reply to Arunshankar Dhandayuthapany
    TI__Guru**** 487215 points

    Hi,

    Strange, after updating the firmware, applying the patch on PDK, could you please confirm you rebuild the SDK, by running "make pdk && make sdk" commands? 

    Regards,

    Brijesh

  • 0 in reply to Brijesh Jadav
    Prodigy 160 points

    Hi Brijesh,

    Just to confirm could you please tell which directory I have to call thsi ? I did clean and rebuild inside vision_apps folder

  • +1 in reply to Arunshankar Dhandayuthapany
    TI__Guru**** 487215 points

    Hi Arunshankar,

    Can you try building it from vision_apps folder? Try below command in sequence.

    1, make pdk

    2, make sdk

    3, make linux_fs_install_sd.

    Regards,

    Brijesh