Hi,TI experts，During the design process, we encountered the following two questions, please help to answer them.
1、In the demo guide for LPDDR4 16 - layer boards, single-end impedance of 40 Ω, differential 80Ω, because it is 32-bit DDR, DDR_CH0_CLK, DDR_CH0_CA0 cable is Y type cable, differential 66 Ω, single end 33 Ω
However, in the document spRACn9b.pdf , the conclusion of 10-layer plate simulation is completely different from the parameters of 16-layer plate design.
Question: how much is the signal impedance controlled for each group?
2、Is there a support list for LPDDR4, EMMC, FASLH(8bit)? Please help to provide.
thank you.
