Hello, TI experts!
Currently, our PCB board uses 10 layers of through-holes for design, and we need your assistance when we encounter problems in LPDDR4.
The status is as follows:
Plan A: TDA4VMid 10 layer reference design, with Allegre software can be opened, but converted to PDAS 9.5 (suffix. PCB) was unsuccessful.
Plan B: TDA4VMid 16 layer board reference design, convert PADS 9.5 success. For LPDDR4 wiring, the design is compressed into 10 layers (wiring remains unchanged) and placed on layers L3, L5, L7, and L9.
Question1: For LPDDR4, the design of 10layer board is different from that of 16layer board (same impedance, different line width and line spacing). Currently, we plan to adopt "Plan B" to deal with it. Shall we use IBS model to simulate and then we can use it? Or must we refer to the design of the 10-layer board for Layout? Or do you have any suggestions?
Question 2:TDA4VMid SOC internal DDR cable length?