TDA4VM: PCIe and TSN Support

Jan Le, 

please see answers to your questions:

1 Does the Linux SDK support PTM, or is there planned support?  

2. Does the RTOS SDK support PTM, or is there planned support?

3. Does the AUTOSAR MCAL support PTM, or is there planned support?

[Jian] Currently there is no support in Linux, RTOS or MCAL drivers for PTM. Please clarify if you are using the PCIe as RC or EP, if RC, then enabling PTM can be simple static register configurations. If EP, then depending on who consumes the PTM in EP, the consumer will need to be programmed to use the PTM time.   

4. The reference manual mentions PCIe QoS is not supported - what features does it support and not support?

[Jian] Device supports mapping of PCIe TC/VC to CBA QoS mechanism based on Order ID and CCHANID. User can configure up to 4 VCs where VC3 is the highest priority. Since this is not a direct PCIe QoS implementation, thus listed under non-supported features.    

Would it be possible to migrate certain Ethernet TSN technologies to PCIe such as PTP and AVB?

[Jian] These are distinct protocols regardless the fact that PTM serves similar purpose as PTP in some sense. But none of the TSN protocols can be directly mapped to PCIe. Even for time sync, PTM only support RC->EP synchronization, and the precision is much higher, typically in ~ns range. If you have a PCIe-based system where multiple devices within the same chassis need to be sync'ed, you can certainly use PTM to sync them, without the need to deal with AVB. 

Since PCIe provides a lot of bandwidth, will traffic with strict timing constraints be a problem?

[Jian] The need of QoS was based on real requirement, where the PCIe serves as the shared data path for multiple high-bandwidth applications. For example, if you have isochronous services such as streaming audio, that shares the same PCIe link that also have camera or storage traffic, then there is always a need to prioritize isochroous traffic.  

Can data latency and jitter be determined for a PCIe link? For example, would it be possible to guarantee an application to application delay across one or multiple PCIe links?

[Jian] No. Similar to USB, you can reserve bandwidth, but it is not a deterministic protocol like a traditional TDM interface. 

Hi Jian,

Thanks for the feedback.

We might have one as an EP and another as an RC. Just a few more questions:

1. I assume as part of the PTM setup the PCIe CPTS module needs to be configured as well?
2. How does PTM determine the propagation delay?
3. Where is the hardware timestamp for PTM taken?
4. Do PTM packets get priority over other traffic to improve accuracy (using TC/VC)?
5. What kind of accuracy can we expect with PTM? Would it be sub 10ns for example?
6. Can non-PTM packets be timestamped in hardware?
7. Is there any realistic way of measuring end to end latency of PCIe communication?
8. Will PTM function when PCIe is in backplane mode?
9. When in backplane mode, will the device acting as the backplane be accessible via PCIe? My assumption is that a driver modification would be required.
10. Is there any performance impact on the CPU when using backplane mode or is the data between the PCIe interfaces rerouted in hardware?
11. Can PCIE0 to PCIE3 be logically linked as one Root Complex? The use case is to transfer data from one end-point to another end-point through e.g. PCIE0 to PCIE1 without too much load on the processor.