Other Parts Discussed in Thread: TCA6424,
Hi, I want to use cpsw9g port 5 to connect with bcm89881 by RGMII.
but when the system bring up,and after i run the vision_apps_init.sh, the "GenericPhy_reset" function will be called all the time.
i'm sure the reason is that "while (hMcm->timerTaskShutDownFlag != true)" this conditions is always be true, which located at enet_mcm.c, in "EnetMcm_periodicTick" function.
but i don't kown why ???????
My SDK version: ti-processor-sdk-rtos-j721e-evm-07_03_00_07
My PDK version: pdk_jacinto_07_03_00_29
My Cpsw9g ports config as below :
RGMII3 --> BCM89881
RGMII5 --> BCM89881
RGMII6 --> BCM89881
RGMII1 --> DP83867
My test data path is TDA4 --> CPSW9G -->RGMII5 --> BCM89881 --> T1 --> T1toRJ45 siwtch --> PC;
I will provide the hardware schematic later。
When the system bringup, run the vision_apps_init.sh ,the log is below:
root@j7-evm:~# root@j7-evm:~# cd /opt/vision_apps root@j7-evm:/opt/vision_apps# source ./vision_apps_init.sh root@j7-evm:/opt/vision_apps# [MCU2_0] 3.444721 s: CIO: Init ... Done !!! [MCU2_0] 3.444790 s: ### CPU Frequency <ORG = 1000000000 Hz>, <NEW = 1000000000 Hz> [MCU2_0] 3.444830 s: APP: Init ... !!! [MCU2_0] 3.444848 s: SCICLIENT: Init ... !!! [MCU2_0] 3.445037 s: SCICLIENT: DMSC FW version [21.1.1--v2021.01a (Terrific Lla] [MCU2_0] 3.445071 s: SCICLIENT: DMSC FW revision 0x15 [MCU2_0] 3.445093 s: SCICLIENT: DMSC FW ABI revision 3.1 [MCU2_0] 3.445115 s: SCICLIENT: Init ... Done !!! [MCU2_0] 3.445136 s: UDMA: Init ... !!! [MCU2_0] 3.446187 s: UDMA: Init ... Done !!! [MCU2_0] 3.446238 s: MEM: Init ... !!! [MCU2_0] 3.446271 s: MEM: Created heap (DDR_SHARED_MEM, id=0, flags=0x00000004) @ e1000000 of size 16777216 bytes !!! [MCU2_0] 3.446324 s: MEM: Created heap (L3_MEM, id=1, flags=0x00000000) @ 3600000 of size 131072 bytes !!! [MCU2_0] 3.446369 s: MEM: Created heap (DDR_NON_CACHE_ME, id=5, flags=0x00000000) @ d8000000 of size 16777216 bytes !!! [MCU2_0] 3.446413 s: MEM: Init ... Done !!! [MCU2_0] 3.446432 s: IPC: Init ... !!! [MCU2_0] 3.446460 s: IPC: 6 CPUs participating in IPC !!! [MCU2_0] 3.446493 s: IPC: Waiting for HLOS to be ready ... !!! [MCU2_0] 30.893546 s: IPC: HLOS is ready !!! [MCU2_0] 30.899093 s: IPC: Init ... Done !!! [MCU2_0] 30.899154 s: APP: Syncing with 5 CPUs ... !!! [MCU2_0] 30.917895 s: APP: Syncing with 5 CPUs ... Done !!! [MCU2_0] 30.918062 s: REMOTE_SERVICE: Init ... !!! [MCU2_0] 30.919871 s: REMOTE_SERVICE: Init ... Done !!! [MCU2_0] 30.919932 s: ETHFW: Init ... !!! [MCU2_0] 30.940989 s: CPSW_9G Test on MAIN NAVSS [MCU2_0] 30.952818 s: [LXC] phyCfg->phyAddr = 12, portNum = 0 [MCU2_0] 30.952875 s: [untouch:liuxianchao] EthFw_initLinkArgs, macPort = 0, vlanCfg portCfi is 0, portPri is 0, portVID is 400 [MCU2_0] 30.953066 s: [LXC] phyCfg->phyAddr = 0, portNum = 2 [MCU2_0] 30.953106 s: [untouch:liuxianchao] EthFw_initLinkArgs, macPort = 2, vlanCfg portCfi is 0, portPri is 2, portVID is 402 [MCU2_0] 30.953490 s: EnetPhy_bindDriver: PHY 0: OUI:2b8094 Model:03 Ver:02 <-> 'generic' : OK [MCU2_0] 30.953582 s: [LXC] phyCfg->phyAddr = 0, portNum = 4 [MCU2_0] 30.953614 s: [untouch:liuxianchao] EthFw_initLinkArgs, macPort = 4, vlanCfg portCfi is 0, portPri is 4, portVID is 404 [MCU2_0] 30.953945 s: EnetPhy_bindDriver: PHY 0: OUI:2b8094 Model:03 Ver:02 <-> 'generic' : OK [MCU2_0] 30.954029 s: [LXC] phyCfg->phyAddr = 1, portNum = 5 [MCU2_0] 30.954060 s: [untouch:liuxianchao] EthFw_initLinkArgs, macPort = 5, vlanCfg portCfi is 0, portPri is 5, portVID is 405 [MCU2_0] 30.954433 s: EnetPhy_bindDriver: PHY 1: OUI:2b8094 Model:03 Ver:02 <-> 'generic' : OK [MCU2_0] 30.954498 s: PHY 0 is alive [MCU2_0] 30.954527 s: PHY 1 is alive [MCU2_0] 30.956292 s: ETHFW: Version : 0.01.01 [MCU2_0] 30.956347 s: ETHFW: Build Date: Sep 26, 2021 [MCU2_0] 30.956397 s: ETHFW: Build Time: 18:20:43 [MCU2_0] 30.956427 s: ETHFW: Commit SHA: a9710bfb [MCU2_0] 30.956456 s: ETHFW: Init ... DONE !!! [MCU2_0] 30.956480 s: ETHFW: Remove server Init ... !!! [MCU2_0] 30.957839 s: Remote demo device (core : mcu2_0) ..... [MCU2_0] 30.957904 s: ETHFW: Remove server Init ... DONE !!! [MCU2_0] 30.963890 s: Host MAC address: 70:ff:76:1d:92:c1 [MCU2_0] 31.007376 s: FVID2: Init ... !!! [MCU2_0] 31.007474 s: FVID2: Init ... Done !!! [MCU2_0] 31.007515 s: DSS: Init ... !!! [MCU2_0] 31.007536 s: DSS: Display type is eDP !!! [MCU2_0] 31.007557 s: DSS: SoC init ... !!! [MCU2_0] 31.007577 s: SCICLIENT: Sciclient_pmSetModuleState module=152 state=2 [MCU2_0] 31.007723 s: SCICLIENT: Sciclient_pmSetModuleState success [MCU2_0] 31.007752 s: SCICLIENT: Sciclient_pmSetModuleState module=297 state=2 [MCU2_0] 31.007890 s: SCICLIENT: Sciclient_pmSetModuleState success [MCU2_0] 31.007915 s: SCICLIENT: Sciclient_pmSetModuleState module=151 state=2 [MCU2_0] 31.008014 s: SCICLIENT: Sciclient_pmSetModuleState success [MCU2_0] 31.008040 s: SCICLIENT: Sciclient_pmSetModuleClkParent module=152 clk=9 parent=11 [MCU2_0] 31.008115 s: SCICLIENT: Sciclient_pmSetModuleClkParent success [MCU2_0] 31.008141 s: SCICLIENT: Sciclient_pmSetModuleClkParent module=152 clk=13 parent=18 [MCU2_0] 31.008207 s: SCICLIENT: Sciclient_pmSetModuleClkParent success [MCU2_0] 31.008232 s: SCICLIENT: Sciclient_pmSetModuleClkParent module=152 clk=1 parent=2 [MCU2_0] 31.008291 s: SCICLIENT: Sciclient_pmSetModuleClkParent success [MCU2_0] 31.008317 s: SCICLIENT: Sciclient_pmSetModuleClkFreq module=152 clk=1 freq=148500000 [MCU2_0] 31.009303 s: SCICLIENT: Sciclient_pmSetModuleClkFreq success [MCU2_0] 31.009339 s: SCICLIENT: Sciclient_pmModuleClkRequest module=152 clk=1 state=2 flag=0 [MCU2_0] 31.009460 s: SCICLIENT: Sciclient_pmModuleClkRequest success [MCU2_0] 31.009492 s: DSS: SoC init ... Done !!! [MCU2_0] 31.009513 s: DSS: Board init ... !!! [MCU2_0] 31.009532 s: DSS: Board init ... Done !!! [MCU2_0] 31.027920 s: DSS: Init ... Done !!! [MCU2_0] 31.027979 s: VHWA: VPAC Init ... !!! [MCU2_0] 31.028005 s: SCICLIENT: Sciclient_pmSetModuleState module=290 state=2 [MCU2_0] 31.028151 s: SCICLIENT: Sciclient_pmSetModuleState success [MCU2_0] 31.028179 s: VHWA: LDC Init ... !!! [MCU2_0] 31.031037 s: VHWA: LDC Init ... Done !!! [MCU2_0] 31.031087 s: VHWA: MSC Init ... !!! [MCU2_0] 31.039282 s: VHWA: MSC Init ... Done !!! [MCU2_0] 31.039330 s: VHWA: NF Init ... !!! [MCU2_0] 31.040792 s: VHWA: NF Init ... Done !!! [MCU2_0] 31.040841 s: VHWA: VISS Init ... !!! [MCU2_0] 31.046551 s: VHWA: VISS Init ... Done !!! [MCU2_0] 31.046602 s: VHWA: VPAC Init ... Done !!! [MCU2_0] 31.046639 s: VX_ZONE_INIT:Enabled [MCU2_0] 31.046661 s: VX_ZONE_ERROR:Enabled [MCU2_0] 31.046680 s: VX_ZONE_WARNING:Enabled [MCU2_0] 31.047726 s: VX_ZONE_INIT:[tivxPlatformCreateTargetId:55] Added target IPU1-0 [MCU2_0] 31.048005 s: VX_ZONE_INIT:[tivxPlatformCreateTargetId:55] Added target VPAC_NF [MCU2_0] 31.048267 s: VX_ZONE_INIT:[tivxPlatformCreateTargetId:55] Added target VPAC_LDC1 [MCU2_0] 31.048570 s: VX_ZONE_INIT:[tivxPlatformCreateTargetId:55] Added target VPAC_MSC1 [MCU2_0] 31.048831 s: VX_ZONE_INIT:[tivxPlatformCreateTargetId:55] Added target VPAC_MSC2 [MCU2_0] 31.049121 s: VX_ZONE_INIT:[tivxPlatformCreateTargetId:55] Added target VPAC_VISS1 [MCU2_0] 31.049457 s: VX_ZONE_INIT:[tivxPlatformCreateTargetId:55] Added target CAPTURE1 [MCU2_0] 31.049759 s: VX_ZONE_INIT:[tivxPlatformCreateTargetId:55] Added target CAPTURE2 [MCU2_0] 31.050039 s: VX_ZONE_INIT:[tivxPlatformCreateTargetId:55] Added target DISPLAY1 [MCU2_0] 31.050324 s: VX_ZONE_INIT:[tivxPlatformCreateTargetId:55] Added target DISPLAY2 [MCU2_0] 31.050646 s: VX_ZONE_INIT:[tivxPlatformCreateTargetId:55] Added target CSITX [MCU2_0] 31.050930 s: VX_ZONE_INIT:[tivxPlatformCreateTargetId:55] Added target CAPTURE3 [MCU2_0] 31.051221 s: VX_ZONE_INIT:[tivxPlatformCreateTargetId:55] Added target CAPTURE4 [MCU2_0] 31.051560 s: VX_ZONE_INIT:[tivxPlatformCreateTargetId:55] Added target CAPTURE5 [MCU2_0] 31.051867 s: VX_ZONE_INIT:[tivxPlatformCreateTargetId:55] Added target CAPTURE6 [MCU2_0] 31.052147 s: VX_ZONE_INIT:[tivxPlatformCreateTargetId:55] Added target CAPTURE7 [MCU2_0] 31.052489 s: VX_ZONE_INIT:[tivxPlatformCreateTargetId:55] Added target CAPTURE8 [MCU2_0] 31.052539 s: VX_ZONE_INIT:[tivxInit:71] Initialization Done !!! [MCU2_0] 31.052567 s: APP: OpenVX Target kernel init ... !!! [MCU2_0] 31.064277 s: APP: OpenVX Target kernel init ... Done !!! [MCU2_0] 31.064334 s: CSI2RX: Init ... !!! [MCU2_0] 31.064353 s: SCICLIENT: Sciclient_pmSetModuleState module=25 state=2 [MCU2_0] 31.064492 s: SCICLIENT: Sciclient_pmSetModuleState success [MCU2_0] 31.064525 s: SCICLIENT: Sciclient_pmSetModuleState module=26 state=2 [MCU2_0] 31.064620 s: SCICLIENT: Sciclient_pmSetModuleState success [MCU2_0] 31.064644 s: SCICLIENT: Sciclient_pmSetModuleState module=27 state=2 [MCU2_0] 31.064721 s: SCICLIENT: Sciclient_pmSetModuleState success [MCU2_0] 31.064747 s: SCICLIENT: Sciclient_pmSetModuleState module=147 state=2 [MCU2_0] 31.064802 s: SCICLIENT: Sciclient_pmSetModuleState success [MCU2_0] 31.064826 s: SCICLIENT: Sciclient_pmSetModuleState module=148 state=2 [MCU2_0] 31.065040 s: SCICLIENT: Sciclient_pmSetModuleState success [MCU2_0] 31.065756 s: CSI2RX: Init ... Done !!! [MCU2_0] 31.065807 s: CSI2TX: Init ... !!! [MCU2_0] 31.065830 s: SCICLIENT: Sciclient_pmSetModuleState module=25 state=2 [MCU2_0] 31.065898 s: SCICLIENT: Sciclient_pmSetModuleState success [MCU2_0] 31.065926 s: SCICLIENT: Sciclient_pmSetModuleState module=28 state=2 [MCU2_0] 31.066013 s: SCICLIENT: Sciclient_pmSetModuleState success [MCU2_0] 31.066038 s: SCICLIENT: Sciclient_pmSetModuleState module=296 state=2 [MCU2_0] 31.066111 s: SCICLIENT: Sciclient_pmSetModuleState success [MCU2_0] 31.066623 s: CSI2TX: Init ... Done !!! [MCU2_0] 31.066669 s: ISS: Init ... !!! [MCU2_0] 31.066695 s: Found sensor IMX390-UB953_D3 at location 0 [MCU2_0] 31.066767 s: LXC 0001111: IssSensor_AR0233_Init, 174, status = 255 [MCU2_0] 31.066803 s: Found sensor AR0233-UB953_MARS at location 1 [MCU2_0] 31.066831 s: Found sensor AR0820-UB953_LI at location 2 [MCU2_0] 31.066857 s: Found sensor UB9xxx_RAW12_TESTPATTERN at location 3 [MCU2_0] 31.066887 s: Found sensor UB96x_UYVY_TESTPATTERN at location 4 [MCU2_0] 31.066915 s: Found sensor GW_AR0233_UYVY at location 5 [MCU2_0] 31.066941 s: IssSensor_Init ... Done !!! [MCU2_0] 31.067011 s: vissRemoteServer_Init ... Done !!! [MCU2_0] 31.067064 s: IttRemoteServer_Init ... Done !!! [MCU2_0] 31.067090 s: UDMA Copy: Init ... !!! [MCU2_0] 31.068553 s: UDMA Copy: Init ... Done !!! [MCU2_0] 31.068606 s: APP: Init ... Done !!! [MCU2_0] 31.068629 s: APP: Run ... !!! [MCU2_0] 31.068650 s: IPC: Starting echo test ... [MCU2_0] 31.071105 s: APP: Run ... Done !!! [MCU2_0] 31.071304 s: [MCU2_0] 31.071404 s: [LXC]: GenericPhy_reset. PHY 0: reset [MCU2_0] 31.071454 s: Bcm89881_config start, master:1, speed:100, loopback:0 [MCU2_0] 31.071501 s: [LXC]: Bcm89881_config hPhy->addr = 0 [MCU2_0] 31.076308 s: [LXC]: hunmaster1111 finished. hPhy->addr = 0 [MCU2_0] 31.076381 s: [LXC]: hunmaster2222 finished. hPhy->addr = 0 [MCU2_0] 31.077948 s: [MCU2_0] CPSW NIMU application, IP address I/F 1: 192.168.10.33 [MCU2_0] 31.078726 s: IPC: Echo status: mpu1_0[x] mcu2_0[s] mcu2_1[.] C66X_1[P] C66X_2[.] C7X_1[.] [MCU2_0] 31.078906 s: IPC: Echo status: mpu1_0[x] mcu2_0[s] mcu2_1[.] C66X_1[P] C66X_2[P] C7X_1[.] [MCU2_0] 31.079026 s: IPC: Echo status: mpu1_0[x] mcu2_0[s] mcu2_1[P] C66X_1[P] C66X_2[P] C7X_1[.] [MCU2_0] 31.079121 s: IPC: Echo status: mpu1_0[x] mcu2_0[s] mcu2_1[P] C66X_1[P] C66X_2[P] C7X_1[P] [MCU2_0] 31.176978 s: [MCU2_0] 31.177043 s: [LXC]: GenericPhy_reset. PHY 0: reset [MCU2_0] 31.177080 s: Bcm89881_config start, master:1, speed:100, loopback:0 [MCU2_0] 31.177122 s: [LXC]: Bcm89881_config hPhy->addr = 0 [MCU2_0] 31.181945 s: [LXC]: hunmaster1111 finished. hPhy->addr = 0 [MCU2_0] 31.181996 s: [LXC]: hunmaster2222 finished. hPhy->addr = 0 [MCU2_0] 31.281963 s: [MCU2_0] 31.282022 s: [LXC]: GenericPhy_reset. PHY 1: reset [MCU2_0] 31.282060 s: Bcm89881_config start, master:1, speed:100, loopback:0 [MCU2_0] 31.282102 s: [LXC]: Bcm89881_config hPhy->addr = 1 [MCU2_0] 31.286927 s: [LXC]: hunmaster1111 finished. hPhy->addr = 1 [MCU2_0] 31.286978 s: [LXC]: hunmaster2222 finished. hPhy->addr = 1 [MCU2_0] 31.401125 s: EthFw: TimeSync PTP enabled [MCU2_0] 33.406126 s: Function:CpswProxyServer_attachExtHandlerCb,HostId:0,CpswType:6 [MCU2_0] 34.775420 s: Function:CpswProxyServer_registerMacHandlerCb,HostId:0,Handle:a32049fc,CoreKey:38acb7e6, MacAddress:70:ff:76:1d:92:c2, FlowIdx:172, FlowIdxOffset:0 [MCU2_0] 34.778503 s: Cpsw_ioctlInternal: CPSW: Registered MAC address.ALE entry:13, Policer Entry:2 [MCU2_0] 36.454411 s: [MCU2_0] 36.454481 s: [LXC]: GenericPhy_reset. PHY 0: reset [MCU2_0] 36.454523 s: Bcm89881_config start, master:1, speed:100, loopback:0 [MCU2_0] 36.454567 s: [LXC]: Bcm89881_config hPhy->addr = 0 [MCU2_0] 36.459372 s: [LXC]: hunmaster1111 finished. hPhy->addr = 0 [MCU2_0] 36.459427 s: [LXC]: hunmaster2222 finished. hPhy->addr = 0 [MCU2_0] 36.559974 s: [MCU2_0] 36.560035 s: [LXC]: GenericPhy_reset. PHY 0: reset [MCU2_0] 36.560074 s: Bcm89881_config start, master:1, speed:100, loopback:0 [MCU2_0] 36.560137 s: [LXC]: Bcm89881_config hPhy->addr = 0 [MCU2_0] 36.564942 s: [LXC]: hunmaster1111 finished. hPhy->addr = 0 [MCU2_0] 36.564995 s: [LXC]: hunmaster2222 finished. hPhy->addr = 0 [MCU2_0] 36.664960 s: [MCU2_0] 36.665017 s: [LXC]: GenericPhy_reset. PHY 1: reset [MCU2_0] 36.665053 s: Bcm89881_config start, master:1, speed:100, loopback:0 [MCU2_0] 36.665096 s: [LXC]: Bcm89881_config hPhy->addr = 1 [MCU2_0] 36.669932 s: [LXC]: hunmaster1111 finished. hPhy->addr = 1 [MCU2_0] 36.669982 s: [LXC]: hunmaster2222 finished. hPhy->addr = 1 [MCU2_0] 41.854407 s: [MCU2_0] 41.854478 s: [LXC]: GenericPhy_reset. PHY 0: reset [MCU2_0] 41.854519 s: Bcm89881_config start, master:1, speed:100, loopback:0 [MCU2_0] 41.854563 s: [LXC]: Bcm89881_config hPhy->addr = 0 [MCU2_0] 41.859391 s: [LXC]: hunmaster1111 finished. hPhy->addr = 0 [MCU2_0] 41.859446 s: [LXC]: hunmaster2222 finished. hPhy->addr = 0 [MCU2_0] 41.959941 s: [MCU2_0] 41.960005 s: [LXC]: GenericPhy_reset. PHY 0: reset [MCU2_0] 41.960044 s: Bcm89881_config start, master:1, speed:100, loopback:0 [MCU2_0] 41.960086 s: [LXC]: Bcm89881_config hPhy->addr = 0 [MCU2_0] 41.964908 s: [LXC]: hunmaster1111 finished. hPhy->addr = 0 [MCU2_0] 41.964960 s: [LXC]: hunmaster2222 finished. hPhy->addr = 0 [MCU2_0] 42.064983 s: [MCU2_0] 42.065039 s: [LXC]: GenericPhy_reset. PHY 1: reset [MCU2_0] 42.065079 s: Bcm89881_config start, master:1, speed:100, loopback:0 [MCU2_0] 42.065122 s: [LXC]: Bcm89881_config hPhy->addr = 1 [MCU2_0] 42.069955 s: [LXC]: hunmaster1111 finished. hPhy->addr = 1 [MCU2_0] 42.070006 s: [LXC]: hunmaster2222 finished. hPhy->addr = 1 [MCU2_0] 47.254405 s: [MCU2_0] 47.254477 s: [LXC]: GenericPhy_reset. PHY 0: reset [MCU2_0] 47.254520 s: Bcm89881_config start, master:1, speed:100, loopback:0 [MCU2_0] 47.254564 s: [LXC]: Bcm89881_config hPhy->addr = 0 [MCU2_0] 47.259411 s: [LXC]: hunmaster1111 finished. hPhy->addr = 0 [MCU2_0] 47.259462 s: [LXC]: hunmaster2222 finished. hPhy->addr = 0 [MCU2_0] 47.359961 s: [MCU2_0] 47.360022 s: [LXC]: GenericPhy_reset. PHY 0: reset [MCU2_0] 47.360063 s: Bcm89881_config start, master:1, speed:100, loopback:0 [MCU2_0] 47.360106 s: [LXC]: Bcm89881_config hPhy->addr = 0 [MCU2_0] 47.364930 s: [LXC]: hunmaster1111 finished. hPhy->addr = 0 [MCU2_0] 47.364983 s: [LXC]: hunmaster2222 finished. hPhy->addr = 0 [MCU2_0] 47.464951 s: [MCU2_0] 47.465013 s: [LXC]: GenericPhy_reset. PHY 1: reset [MCU2_0] 47.465052 s: Bcm89881_config start, master:1, speed:100, loopback:0 [MCU2_0] 47.465096 s: [LXC]: Bcm89881_config hPhy->addr = 1 [MCU2_0] 47.469918 s: [LXC]: hunmaster1111 finished. hPhy->addr = 1 [MCU2_0] 47.469971 s: [LXC]: hunmaster2222 finished. hPhy->addr = 1 [MCU2_0] 52.654409 s: [MCU2_0] 52.654479 s: [LXC]: GenericPhy_reset. PHY 0: reset [MCU2_0] 52.654522 s: Bcm89881_config start, master:1, speed:100, loopback:0 [MCU2_0] 52.654564 s: [LXC]: Bcm89881_config hPhy->addr = 0 [MCU2_0] 52.659384 s: [LXC]: hunmaster1111 finished. hPhy->addr = 0 [MCU2_0] 52.659439 s: [LXC]: hunmaster2222 finished. hPhy->addr = 0 [MCU2_0] 52.759984 s: [MCU2_0] 52.760047 s: [LXC]: GenericPhy_reset. PHY 0: reset [MCU2_0] 52.760086 s: Bcm89881_config start, master:1, speed:100, loopback:0 [MCU2_0] 52.760153 s: [LXC]: Bcm89881_config hPhy->addr = 0 [MCU2_0] 52.764954 s: [LXC]: hunmaster1111 finished. hPhy->addr = 0 [MCU2_0] 52.765005 s: [LXC]: hunmaster2222 finished. hPhy->addr = 0 [MCU2_0] 52.864970 s: [MCU2_0] 52.865024 s: [LXC]: GenericPhy_reset. PHY 1: reset [MCU2_0] 52.865062 s: Bcm89881_config start, master:1, speed:100, loopback:0 [MCU2_0] 52.865103 s: [LXC]: Bcm89881_config hPhy->addr = 1 [MCU2_0] 52.869940 s: [LXC]: hunmaster1111 finished. hPhy->addr = 1 [MCU2_0] 52.869990 s: [LXC]: hunmaster2222 finished. hPhy->addr = 1 [MCU2_0] 58.054404 s: [MCU2_0] 58.054472 s: [LXC]: GenericPhy_reset. PHY 0: reset [MCU2_0] 58.054511 s: Bcm89881_config start, master:1, speed:100, loopback:0 [MCU2_0] 58.054552 s: [LXC]: Bcm89881_config hPhy->addr = 0 [MCU2_0] 58.059401 s: [LXC]: hunmaster1111 finished. hPhy->addr = 0 [MCU2_0] 58.059457 s: [LXC]: hunmaster2222 finished. hPhy->addr = 0 [MCU2_0] 58.159947 s: [MCU2_0] 58.160008 s: [LXC]: GenericPhy_reset. PHY 0: reset [MCU2_0] 58.160047 s: Bcm89881_config start, master:1, speed:100, loopback:0 [MCU2_0] 58.160090 s: [LXC]: Bcm89881_config hPhy->addr = 0 [MCU2_0] 58.164918 s: [LXC]: hunmaster1111 finished. hPhy->addr = 0 [MCU2_0] 58.164967 s: [LXC]: hunmaster2222 finished. hPhy->addr = 0 [MCU2_0] 58.264933 s: [MCU2_0] 58.264989 s: [LXC]: GenericPhy_reset. PHY 1: reset [MCU2_0] 58.265026 s: Bcm89881_config start, master:1, speed:100, loopback:0 [MCU2_0] 58.265071 s: [LXC]: Bcm89881_config hPhy->addr = 1 [MCU2_0] 58.269903 s: [LXC]: hunmaster1111 finished. hPhy->addr = 1 [MCU2_0] 58.269952 s: [LXC]: hunmaster2222 finished. hPhy->addr = 1 [MCU2_0] 63.454412 s: [MCU2_0] 63.454484 s: [LXC]: GenericPhy_reset. PHY 0: reset [MCU2_0] 63.454525 s: Bcm89881_config start, master:1, speed:100, loopback:0 [MCU2_0] 63.454570 s: [LXC]: Bcm89881_config hPhy->addr = 0 [MCU2_0] 63.459373 s: [LXC]: hunmaster1111 finished. hPhy->addr = 0 [MCU2_0] 63.459430 s: [LXC]: hunmaster2222 finished. hPhy->addr = 0 [MCU2_0] 63.559971 s: [MCU2_0] 63.560031 s: [LXC]: GenericPhy_reset. PHY 0: reset [MCU2_1] 3.547293 s: CIO: Init ... Done !!! [MCU2_1] 3.547358 s: ### CPU Frequency <ORG = 1000000000 Hz>, <NEW = 1000000000 Hz> [MCU2_1] 3.547399 s: APP: Init ... !!! [MCU2_1] 3.547419 s: SCICLIENT: Init ... !!! [MCU2_1] 3.547605 s: SCICLIENT: DMSC FW version [21.1.1--v2021.01a (Terrific Lla] [MCU2_1] 3.547639 s: SCICLIENT: DMSC FW revision 0x15 [MCU2_1] 3.547662 s: SCICLIENT: DMSC FW ABI revision 3.1 [MCU2_1] 3.547686 s: SCICLIENT: Init ... Done !!! [MCU2_1] 3.547707 s: UDMA: Init ... !!! [MCU2_1] 3.548806 s: UDMA: Init ... Done !!! [MCU2_1] 3.548853 s: MEM: Init ... !!! [MCU2_1] 3.548889 s: MEM: Created heap (DDR_SHARED_MEM, id=0, flags=0x00000004) @ e2000000 of size 16777216 bytes !!! [MCU2_1] 3.548941 s: MEM: Created heap (L3_MEM, id=1, flags=0x00000001) @ 3620000 of size 131072 bytes !!! [MCU2_1] 3.548991 s: MEM: Created heap (DDR_NON_CACHE_ME, id=5, flags=0x00000000) @ d9000000 of size 117440512 bytes !!! [MCU2_1] 3.549037 s: MEM: Init ... Done !!! [MCU2_1] 3.549058 s: IPC: Init ... !!! [MCU2_1] 3.549086 s: IPC: 6 CPUs participating in IPC !!! [MCU2_1] 3.549123 s: IPC: Waiting for HLOS to be ready ... !!! [MCU2_1] 30.912499 s: IPC: HLOS is ready !!! [MCU2_1] 30.917801 s: IPC: Init ... Done !!! [MCU2_1] 30.917855 s: APP: Syncing with 5 CPUs ... !!! [MCU2_1] 30.917892 s: APP: Syncing with 5 CPUs ... Done !!! [MCU2_1] 30.917920 s: REMOTE_SERVICE: Init ... !!! [MCU2_1] 30.919735 s: REMOTE_SERVICE: Init ... Done !!! [MCU2_1] 30.919796 s: FVID2: Init ... !!! [MCU2_1] 30.919855 s: FVID2: Init ... Done !!! [MCU2_1] 30.919884 s: VHWA: DMPAC: Init ... !!! [MCU2_1] 30.919904 s: SCICLIENT: Sciclient_pmSetModuleState module=48 state=2 [MCU2_1] 30.920042 s: SCICLIENT: Sciclient_pmSetModuleState success [MCU2_1] 30.920073 s: SCICLIENT: Sciclient_pmSetModuleState module=305 state=2 [MCU2_1] 30.920518 s: SCICLIENT: Sciclient_pmSetModuleState success [MCU2_1] 30.920552 s: VHWA: DOF Init ... !!! [MCU2_1] 30.927878 s: VHWA: DOF Init ... Done !!! [MCU2_1] 30.927928 s: VHWA: SDE Init ... !!! [MCU2_1] 30.929997 s: VHWA: SDE Init ... Done !!! [MCU2_1] 30.930041 s: VHWA: DMPAC: Init ... Done !!! [MCU2_1] 30.930066 s: VHWA: Codec: Init ... !!! [MCU2_1] 30.930086 s: VHWA: VDEC Init ... !!! [MCU2_1] 30.943672 s: VHWA: VDEC Init ... Done !!! [MCU2_1] 30.943725 s: VHWA: VENC Init ... !!! [MCU2_1] 30.943868 s: MM_ENC_Init: No OCM RAM pool available, fallback to DDR mode for above mp params [MCU2_1] 30.985244 s: VHWA: VENC Init ... Done !!! [MCU2_1] 30.985293 s: VHWA: Init ... Done !!! [MCU2_1] 30.985329 s: VX_ZONE_INIT:Enabled [MCU2_1] 30.985352 s: VX_ZONE_ERROR:Enabled [MCU2_1] 30.985409 s: VX_ZONE_WARNING:Enabled [MCU2_1] 30.986343 s: VX_ZONE_INIT:[tivxPlatformCreateTargetId:55] Added target DMPAC_SDE [MCU2_1] 30.986597 s: VX_ZONE_INIT:[tivxPlatformCreateTargetId:55] Added target DMPAC_DOF [MCU2_1] 30.986810 s: VX_ZONE_INIT:[tivxPlatformCreateTargetId:55] Added target VDEC1 [MCU2_1] 30.987020 s: VX_ZONE_INIT:[tivxPlatformCreateTargetId:55] Added target VDEC2 [MCU2_1] 30.987226 s: VX_ZONE_INIT:[tivxPlatformCreateTargetId:55] Added target VENC1 [MCU2_1] 30.987474 s: VX_ZONE_INIT:[tivxPlatformCreateTargetId:55] Added target VENC2 [MCU2_1] 30.987527 s: VX_ZONE_INIT:[tivxInit:71] Initialization Done !!! [MCU2_1] 30.987556 s: APP: OpenVX Target kernel init ... !!! [MCU2_1] 30.987901 s: APP: OpenVX Target kernel init ... Done !!! [MCU2_1] 30.987943 s: UDMA Copy: Init ... !!! [MCU2_1] 30.989398 s: UDMA Copy: Init ... Done !!! [MCU2_1] 30.989452 s: APP: Init ... Done !!! [MCU2_1] 30.989477 s: APP: Run ... !!! [MCU2_1] 30.989497 s: IPC: Starting echo test ... [MCU2_1] 30.991617 s: APP: Run ... Done !!! [MCU2_1] 30.992721 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[s] C66X_1[P] C66X_2[.] C7X_1[.] [MCU2_1] 30.992805 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[s] C66X_1[P] C66X_2[P] C7X_1[.] [MCU2_1] 30.992868 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[s] C66X_1[P] C66X_2[P] C7X_1[P] [MCU2_1] 31.078410 s: IPC: Echo status: mpu1_0[x] mcu2_0[P] mcu2_1[s] C66X_1[P] C66X_2[P] C7X_1[P] [C6x_1 ] 3.655613 s: CIO: Init ... Done !!! [C6x_1 ] 3.655645 s: ### CPU Frequency <ORG = 1350000000 Hz>, <NEW = 1350000000 Hz> [C6x_1 ] 3.655658 s: APP: Init ... !!! [C6x_1 ] 3.655665 s: SCICLIENT: Init ... !!! [C6x_1 ] 3.655846 s: SCICLIENT: DMSC FW version [21.1.1--v2021.01a (Terrific Lla] [C6x_1 ] 3.655857 s: SCICLIENT: DMSC FW revision 0x15 [C6x_1 ] 3.655865 s: SCICLIENT: DMSC FW ABI revision 3.1 [C6x_1 ] 3.655875 s: SCICLIENT: Init ... Done !!! [C6x_1 ] 3.655883 s: UDMA: Init ... !!! [C6x_1 ] 3.657038 s: UDMA: Init ... Done !!! [C6x_1 ] 3.657061 s: MEM: Init ... !!! [C6x_1 ] 3.657072 s: MEM: Created heap (DDR_SHARED_MEM, id=0, flags=0x00000004) @ e4000000 of size 16777216 bytes !!! [C6x_1 ] 3.657088 s: MEM: Created heap (L2_MEM, id=2, flags=0x00000001) @ 800000 of size 229376 bytes !!! [C6x_1 ] 3.657103 s: MEM: Created heap (DDR_SCRATCH_MEM, id=4, flags=0x00000001) @ e5000000 of size 50331648 bytes !!! [C6x_1 ] 3.657118 s: MEM: Init ... Done !!! [C6x_1 ] 3.657126 s: IPC: Init ... !!! [C6x_1 ] 3.657138 s: IPC: 6 CPUs participating in IPC !!! [C6x_1 ] 3.657151 s: IPC: Waiting for HLOS to be ready ... !!! [C6x_1 ] 29.818252 s: IPC: HLOS is ready !!! [C6x_1 ] 29.821978 s: IPC: Init ... Done !!! [C6x_1 ] 29.822013 s: APP: Syncing with 5 CPUs ... !!! [C6x_1 ] 30.917892 s: APP: Syncing with 5 CPUs ... Done !!! [C6x_1 ] 30.917906 s: REMOTE_SERVICE: Init ... !!! [C6x_1 ] 30.918678 s: REMOTE_SERVICE: Init ... Done !!! [C6x_1 ] 30.918720 s: VX_ZONE_INIT:Enabled [C6x_1 ] 30.918733 s: VX_ZONE_ERROR:Enabled [C6x_1 ] 30.918743 s: VX_ZONE_WARNING:Enabled [C6x_1 ] 30.919649 s: VX_ZONE_INIT:[tivxInit:71] Initialization Done !!! [C6x_1 ] 30.919670 s: APP: OpenVX Target kernel init ... !!! [C6x_1 ] 30.919953 s: APP: OpenVX Target kernel init ... Done !!! [C6x_1 ] 30.919971 s: UDMA Copy: Init ... !!! [C6x_1 ] 30.923216 s: UDMA Copy: Init ... Done !!! [C6x_1 ] 30.923234 s: APP: Init ... Done !!! [C6x_1 ] 30.923928 s: APP: Run ... !!! [C6x_1 ] 30.923938 s: IPC: Starting echo test ... [C6x_1 ] 30.925027 s: APP: Run ... Done !!! [C6x_1 ] 30.925348 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[x] C66X_1[s] C66X_2[x] C7X_1[P] [C6x_1 ] 30.925759 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[x] C66X_1[s] C66X_2[P] C7X_1[P] [C6x_1 ] 30.992519 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[P] C66X_1[s] C66X_2[P] C7X_1[P] [C6x_1 ] 31.078269 s: IPC: Echo status: mpu1_0[x] mcu2_0[P] mcu2_1[P] C66X_1[s] C66X_2[P] C7X_1[P] [C6x_2 ] 3.740178 s: CIO: Init ... Done !!! [C6x_2 ] 3.740211 s: ### CPU Frequency <ORG = 1350000000 Hz>, <NEW = 1350000000 Hz> [C6x_2 ] 3.740224 s: APP: Init ... !!! [C6x_2 ] 3.740232 s: SCICLIENT: Init ... !!! [C6x_2 ] 3.740413 s: SCICLIENT: DMSC FW version [21.1.1--v2021.01a (Terrific Lla] [C6x_2 ] 3.740425 s: SCICLIENT: DMSC FW revision 0x15 [C6x_2 ] 3.740434 s: SCICLIENT: DMSC FW ABI revision 3.1 [C6x_2 ] 3.740443 s: SCICLIENT: Init ... Done !!! [C6x_2 ] 3.740452 s: UDMA: Init ... !!! [C6x_2 ] 3.741614 s: UDMA: Init ... Done !!! [C6x_2 ] 3.741637 s: MEM: Init ... !!! [C6x_2 ] 3.741648 s: MEM: Created heap (DDR_SHARED_MEM, id=0, flags=0x00000004) @ e8000000 of size 16777216 bytes !!! [C6x_2 ] 3.741665 s: MEM: Created heap (L2_MEM, id=2, flags=0x00000001) @ 800000 of size 229376 bytes !!! [C6x_2 ] 3.741680 s: MEM: Created heap (DDR_SCRATCH_MEM, id=4, flags=0x00000001) @ e9000000 of size 50331648 bytes !!! [C6x_2 ] 3.741696 s: MEM: Init ... Done !!! [C6x_2 ] 3.741704 s: IPC: Init ... !!! [C6x_2 ] 3.741717 s: IPC: 6 CPUs participating in IPC !!! [C6x_2 ] 3.741730 s: IPC: Waiting for HLOS to be ready ... !!! [C6x_2 ] 29.967487 s: IPC: HLOS is ready !!! [C6x_2 ] 29.971044 s: IPC: Init ... Done !!! [C6x_2 ] 29.971074 s: APP: Syncing with 5 CPUs ... !!! [C6x_2 ] 30.917892 s: APP: Syncing with 5 CPUs ... Done !!! [C6x_2 ] 30.917906 s: REMOTE_SERVICE: Init ... !!! [C6x_2 ] 30.918688 s: REMOTE_SERVICE: Init ... Done !!! [C6x_2 ] 30.918726 s: VX_ZONE_INIT:Enabled [C6x_2 ] 30.918743 s: VX_ZONE_ERROR:Enabled [C6x_2 ] 30.918752 s: VX_ZONE_WARNING:Enabled [C6x_2 ] 30.919644 s: VX_ZONE_INIT:[tivxInit:71] Initialization Done !!! [C6x_2 ] 30.919664 s: APP: OpenVX Target kernel init ... !!! [C6x_2 ] 30.919958 s: APP: OpenVX Target kernel init ... Done !!! [C6x_2 ] 30.919978 s: UDMA Copy: Init ... !!! [C6x_2 ] 30.923495 s: UDMA Copy: Init ... Done !!! [C6x_2 ] 30.923513 s: APP: Init ... Done !!! [C6x_2 ] 30.924209 s: APP: Run ... !!! [C6x_2 ] 30.924231 s: IPC: Starting echo test ... [C6x_2 ] 30.925416 s: APP: Run ... Done !!! [C6x_2 ] 30.925764 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[x] C66X_1[P] C66X_2[s] C7X_1[.] [C6x_2 ] 30.925804 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[x] C66X_1[P] C66X_2[s] C7X_1[P] [C6x_2 ] 30.992545 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[P] C66X_1[P] C66X_2[s] C7X_1[P] [C6x_2 ] 31.078305 s: IPC: Echo status: mpu1_0[x] mcu2_0[P] mcu2_1[P] C66X_1[P] C66X_2[s] C7X_1[P] [C7x_1 ] 3.939633 s: CIO: Init ... Done !!! [C7x_1 ] 3.939655 s: ### CPU Frequency <ORG = 1000000000 Hz>, <NEW = 1000000000 Hz> [C7x_1 ] 3.939671 s: APP: Init ... !!! [C7x_1 ] 3.939678 s: SCICLIENT: Init ... !!! [C7x_1 ] 3.939847 s: SCICLIENT: DMSC FW version [21.1.1--v2021.01a (Terrific Lla] [C7x_1 ] 3.939861 s: SCICLIENT: DMSC FW revision 0x15 [C7x_1 ] 3.939871 s: SCICLIENT: DMSC FW ABI revision 3.1 [C7x_1 ] 3.939881 s: SCICLIENT: Init ... Done !!! [C7x_1 ] 3.939889 s: UDMA: Init ... !!! [C7x_1 ] 3.940731 s: UDMA: Init ... Done !!! [C7x_1 ] 3.940743 s: MEM: Init ... !!! [C7x_1 ] 3.940753 s: MEM: Created heap (DDR_SHARED_MEM, id=0, flags=0x00000004) @ 100000000 of size 1073741824 bytes !!! [C7x_1 ] 3.940773 s: MEM: Created heap (L3_MEM, id=1, flags=0x00000001) @ 70020000 of size 8159232 bytes !!! [C7x_1 ] 3.940791 s: MEM: Created heap (L2_MEM, id=2, flags=0x00000001) @ 64800000 of size 491520 bytes !!! [C7x_1 ] 3.940808 s: MEM: Created heap (L1_MEM, id=3, flags=0x00000001) @ 64e00000 of size 16384 bytes !!! [C7x_1 ] 3.940825 s: MEM: Created heap (DDR_SCRATCH_MEM, id=4, flags=0x00000001) @ ec000000 of size 268435456 bytes !!! [C7x_1 ] 3.940843 s: MEM: Init ... Done !!! [C7x_1 ] 3.940850 s: IPC: Init ... !!! [C7x_1 ] 3.940860 s: IPC: 6 CPUs participating in IPC !!! [C7x_1 ] 3.940872 s: IPC: Waiting for HLOS to be ready ... !!! [C7x_1 ] 30.375878 s: IPC: HLOS is ready !!! [C7x_1 ] 30.377895 s: IPC: Init ... Done !!! [C7x_1 ] 30.377909 s: APP: Syncing with 5 CPUs ... !!! [C7x_1 ] 30.917893 s: APP: Syncing with 5 CPUs ... Done !!! [C7x_1 ] 30.917910 s: REMOTE_SERVICE: Init ... !!! [C7x_1 ] 30.918233 s: REMOTE_SERVICE: Init ... Done !!! [C7x_1 ] 30.918255 s: VX_ZONE_INIT:Enabled [C7x_1 ] 30.918265 s: VX_ZONE_ERROR:Enabled [C7x_1 ] 30.918275 s: VX_ZONE_WARNING:Enabled [C7x_1 ] 30.918520 s: VX_ZONE_INIT:[tivxInit:71] Initialization Done !!! [C7x_1 ] 30.918534 s: APP: OpenVX Target kernel init ... !!! [C7x_1 ] 30.918617 s: APP: OpenVX Target kernel init ... Done !!! [C7x_1 ] 30.918631 s: APP: Init ... Done !!! [C7x_1 ] 30.918640 s: APP: Run ... !!! [C7x_1 ] 30.918648 s: IPC: Starting echo test ... [C7x_1 ] 30.919117 s: APP: Run ... Done !!! [C7x_1 ] 30.925359 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[x] C66X_1[P] C66X_2[x] C7X_1[s] [C7x_1 ] 30.925756 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[x] C66X_1[P] C66X_2[P] C7X_1[s] [C7x_1 ] 30.992565 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[P] C66X_1[P] C66X_2[P] C7X_1[s] [C7x_1 ] 31.078327 s: IPC: Echo status: mpu1_0[x] mcu2_0[P] mcu2_1[P] C66X_1[P] C66X_2[P] C7X_1[s] [MCU2_0] 95.854409 s: [MCU2_0] 95.854481 s: [LXC]: GenericPhy_reset. PHY 0: reset [MCU2_0] 95.854519 s: Bcm89881_config start, master:1, speed:100, loopback:0 [MCU2_0] 95.854563 s: [LXC]: Bcm89881_config hPhy->addr = 0 [MCU2_0] 95.859387 s: [LXC]: hunmaster1111 finished. hPhy->addr = 0 [MCU2_0] 95.859445 s: [LXC]: hunmaster2222 finished. hPhy->addr = 0 [MCU2_0] 95.959932 s: [MCU2_0] 95.959995 s: [LXC]: GenericPhy_reset. PHY 0: reset [MCU2_0] 95.960034 s: Bcm89881_config start, master:1, speed:100, loopback:0 [MCU2_0] 95.960076 s: [LXC]: Bcm89881_config hPhy->addr = 0 [MCU2_0] 95.964904 s: [LXC]: hunmaster1111 finished. hPhy->addr = 0 [MCU2_0] 95.964960 s: [LXC]: hunmaster2222 finished. hPhy->addr = 0 [MCU2_0] 96.064978 s: [MCU2_0] 96.065034 s: [LXC]: GenericPhy_reset. PHY 1: reset [MCU2_0] 96.065074 s: Bcm89881_config start, master:1, speed:100, loopback:0 [MCU2_0] 96.065115 s: [LXC]: Bcm89881_config hPhy->addr = 1 [MCU2_0] 96.069949 s: [LXC]: hunmaster1111 finished. hPhy->addr = 1 [MCU2_0] 96.069998 s: [LXC]: hunmaster2222 finished. hPhy->addr = 1 root@j7-evm:/opt/vision_apps# root@j7-evm:/opt/vision_apps# [MCU2_0] 101.254408 s: [MCU2_0] 101.254477 s: [LXC]: GenericPhy_reset. PHY 0: reset [MCU2_0] 101.254517 s: Bcm89881_config start, master:1, speed:100, loopback:0 [MCU2_0] 101.254561 s: [LXC]: Bcm89881_config hPhy->addr = 0 [MCU2_0] 101.259405 s: [LXC]: hunmaster1111 finished. hPhy->addr = 0 [MCU2_0] 101.259457 s: [LXC]: hunmaster2222 finished. hPhy->addr = 0 [MCU2_0] 101.359954 s: [MCU2_0] 101.360012 s: [LXC]: GenericPhy_reset. PHY 0: reset [MCU2_0] 101.360051 s: Bcm89881_config start, master:1, speed:100, loopback:0 [MCU2_0] 101.360096 s: [LXC]: Bcm89881_config hPhy->addr = 0 [MCU2_0] 101.364925 s: [LXC]: hunmaster1111 finished. hPhy->addr = 0 [MCU2_0] 101.364981 s: [LXC]: hunmaster2222 finished. hPhy->addr = 0 [MCU2_0] 101.464944 s: [MCU2_0] 101.465013 s: [LXC]: GenericPhy_reset. PHY 1: reset [MCU2_0] 101.465055 s: Bcm89881_config start, master:1, speed:100, loopback:0 [MCU2_0] 101.465099 s: [LXC]: Bcm89881_config hPhy->addr = 1 [MCU2_0] 101.469912 s: [LXC]: hunmaster1111 finished. hPhy->addr = 1 [MCU2_0] 101.469965 s: [LXC]: hunmaster2222 finished. hPhy->addr = 1 root@j7-evm:/opt/vision_apps# root@j7-evm:/opt/vision_apps# [MCU2_0] 106.654407 s: [MCU2_0] 106.654477 s: [LXC]: GenericPhy_reset. PHY 0: reset [MCU2_0] 106.654518 s: Bcm89881_config start, master:1, speed:100, loopback:0 [MCU2_0] 106.654560 s: [LXC]: Bcm89881_config hPhy->addr = 0 [MCU2_0] 106.659381 s: [LXC]: hunmaster1111 finished. hPhy->addr = 0 [MCU2_0] 106.659435 s: [LXC]: hunmaster2222 finished. hPhy->addr = 0 [MCU2_0] 106.759976 s: [MCU2_0] 106.760042 s: [LXC]: GenericPhy_reset. PHY 0: reset [MCU2_0] 106.760081 s: Bcm89881_config start, master:1, speed:100, loopback:0 [MCU2_0] 106.760146 s: [LXC]: Bcm89881_config hPhy->addr = 0 [MCU2_0] 106.764947 s: [LXC]: hunmaster1111 finished. hPhy->addr = 0 [MCU2_0] 106.765004 s: [LXC]: hunmaster2222 finished. hPhy->addr = 0 [MCU2_0] 106.864964 s: [MCU2_0] 106.865022 s: [LXC]: GenericPhy_reset. PHY 1: reset [MCU2_0] 106.865061 s: Bcm89881_config start, master:1, speed:100, loopback:0 [MCU2_0] 106.865102 s: [LXC]: Bcm89881_config hPhy->addr = 1 [MCU2_0] 106.869932 s: [LXC]: hunmaster1111 finished. hPhy->addr = 1 [MCU2_0] 106.869983 s: [LXC]: hunmaster2222 finished. hPhy->addr = 1 root@j7-evm:/opt/vision_apps# ^C root@j7-evm:/opt/vision_apps# CTRL-A Z for help | 115200 8N1 | NOR | Minicom 2.7.1 | VT102 | Offline | ttyUSB0
The pdk_patch 1:
commit 04193e5764b58195255051114a2d2ea6007f89b0
Author: liuxianchao <liuxianchao@untouch-tech.com>
Date: Fri Sep 24 10:39:26 2021 +0800
push test code for cpsw9g rgmii5
diff --git a/packages/ti/board/src/devices/common/common.c b/packages/ti/board/src/devices/common/common.c
index 600aeed..4e2ae7c 100755
--- a/packages/ti/board/src/devices/common/common.c
+++ b/packages/ti/board/src/devices/common/common.c
@@ -40,6 +40,17 @@
#include "common.h"
+#include <ti/csl/soc.h>
+#include <ti/csl/csl_types.h>
+#include <ti/drv/gpio/GPIO.h>
+#include <ti/drv/gpio/soc/GPIO_soc.h>
+#include <ti/drv/gpio/test/led_blink/src/GPIO_board.h>
+
+/*
+ TODO:
+ PHY3_RST_N: low --> high
+*/
+
/**
* \brief Delay generation function
*
diff --git a/packages/ti/board/src/devices/fpd/ds90ub960.c b/packages/ti/board/src/devices/fpd/ds90ub960.c
index da1a5ea..ad856eb 100755
--- a/packages/ti/board/src/devices/fpd/ds90ub960.c
+++ b/packages/ti/board/src/devices/fpd/ds90ub960.c
@@ -674,6 +674,7 @@ Board_STATUS Board_fpdUb960ReadReg(void *handle,
return ret;
}
+#define UNTOUCH
/**
* \brief Get ub960 i2c address.
*
@@ -694,8 +695,13 @@ void Board_fpdU960GetI2CAddr(uint8_t *chNum,
//J7_TODO: Need to update to make it generic across the devices and platforms
if (csiInst == BOARD_CSI_INST_0)
{
+#ifdef UNTOUCH
+ *chNum = 3U;
+ *i2cAddr = 0x3AU;
+#else
*chNum = 6U;
*i2cAddr = 0x3DU;
+#endif
}
else if (csiInst == BOARD_CSI_INST_1)
{
diff --git a/packages/ti/board/src/j721e_evm/J721E_pinmux_data_gesi_cpsw9g.c b/packages/ti/board/src/j721e_evm/J721E_pinmux_data_gesi_cpsw9g.c
index 4745d2b..64c6b82 100755
--- a/packages/ti/board/src/j721e_evm/J721E_pinmux_data_gesi_cpsw9g.c
+++ b/packages/ti/board/src/j721e_evm/J721E_pinmux_data_gesi_cpsw9g.c
@@ -23,10 +23,10 @@
static pinmuxPerCfg_t gCpsw9g0PinCfg[] =
{
/* MyCPSW9G3 -> CLKOUT -> AA25 */
- {
- PIN_PRG0_PRU1_GPO10, PIN_MODE(0) | \
- ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))
- },
+ // {
+ // PIN_PRG0_PRU1_GPO10, PIN_MODE(0) | \
+ // ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))
+ // },
{PINMUX_END}
};
@@ -36,14 +36,16 @@ static pinmuxModuleCfg_t gCpsw9gPinCfg[] =
{PINMUX_END}
};
-
+/*
+ TODO: 配置PHY复位引脚，I2C扩展芯片P20
+*/
static pinmuxPerCfg_t gGpio0PinCfg[] =
{
/* MyGPIO0 -> GPIO0_96 -> T23 */
- {
- PIN_RGMII5_RD0, PIN_MODE(7) | \
- ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
- },
+ // {
+ // PIN_RGMII5_RD0, PIN_MODE(7) | \
+ // ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
+ // },
/* MyGPIO0 -> GPIO0_104 -> W26 */
{
PIN_RGMII6_RXC, PIN_MODE(7) | \
@@ -74,6 +76,21 @@ static pinmuxPerCfg_t gMdio0PinCfg[] =
{PINMUX_END}
};
+// static pinmuxPerCfg_t gMdio0PinCfg[] =
+// {
+// /* MyMDIO1 -> PIN_PRG1_MDIO0_MDC -> AD18 */
+// {
+// PIN_PRG1_MDIO0_MDC, PIN_MODE(0) | \
+// ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))
+// },
+// /* MyMDIO1 -> PIN_PRG1_MDIO0_MDIO -> AD19 */
+// {
+// PIN_PRG1_MDIO0_MDIO, PIN_MODE(0) | \
+// ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
+// },
+// {PINMUX_END}
+// };
+
static pinmuxModuleCfg_t gMdioPinCfg[] =
{
{0, TRUE, gMdio0PinCfg},
@@ -276,67 +293,132 @@ static pinmuxPerCfg_t gRgmii1PinCfg[] =
{PINMUX_END}
};
-static pinmuxPerCfg_t gRgmii2PinCfg[] =
+// static pinmuxPerCfg_t gRgmii2PinCfg[] =
+// {
+// /* MyRGMII2 -> RGMII2_RD0 -> AE22 */
+// {
+// PIN_PRG1_PRU1_GPO0, PIN_MODE(4) | \
+// ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
+// },
+// /* MyRGMII2 -> RGMII2_RD1 -> AG23 */
+// {
+// PIN_PRG1_PRU1_GPO1, PIN_MODE(4) | \
+// ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
+// },
+// /* MyRGMII2 -> RGMII2_RD2 -> AF23 */
+// {
+// PIN_PRG1_PRU1_GPO2, PIN_MODE(4) | \
+// ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
+// },
+// /* MyRGMII2 -> RGMII2_RD3 -> AD23 */
+// {
+// PIN_PRG1_PRU1_GPO3, PIN_MODE(4) | \
+// ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
+// },
+// /* MyRGMII2 -> RGMII2_RXC -> AE23 */
+// {
+// PIN_PRG1_PRU1_GPO6, PIN_MODE(4) | \
+// ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
+// },
+// /* MyRGMII2 -> RGMII2_RX_CTL -> AH24 */
+// {
+// PIN_PRG1_PRU1_GPO4, PIN_MODE(4) | \
+// ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
+// },
+// /* MyRGMII2 -> RGMII2_TD0 -> AJ25 */
+// {
+// PIN_PRG1_PRU1_GPO11, PIN_MODE(4) | \
+// ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))
+// },
+// /* MyRGMII2 -> RGMII2_TD1 -> AH25 */
+// {
+// PIN_PRG1_PRU1_GPO12, PIN_MODE(4) | \
+// ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))
+// },
+// /* MyRGMII2 -> RGMII2_TD2 -> AG25 */
+// {
+// PIN_PRG1_PRU1_GPO13, PIN_MODE(4) | \
+// ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))
+// },
+// /* MyRGMII2 -> RGMII2_TD3 -> AH26 */
+// {
+// PIN_PRG1_PRU1_GPO14, PIN_MODE(4) | \
+// ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))
+// },
+// /* MyRGMII2 -> RGMII2_TXC -> AJ26 */
+// {
+// PIN_PRG1_PRU1_GPO16, PIN_MODE(4) | \
+// ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
+// },
+// /* MyRGMII2 -> RGMII2_TX_CTL -> AJ27 */
+// {
+// PIN_PRG1_PRU1_GPO15, PIN_MODE(4) | \
+// ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
+// },
+// {PINMUX_END}
+// };
+
+static pinmuxPerCfg_t gRgmii5PinCfg[] =
{
- /* MyRGMII2 -> RGMII2_RD0 -> AE22 */
+ /* MyRGMII5 -> RGMII5_RD0 */
{
- PIN_PRG1_PRU1_GPO0, PIN_MODE(4) | \
+ PIN_RGMII5_RD0, PIN_MODE(0) | \
((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
},
- /* MyRGMII2 -> RGMII2_RD1 -> AG23 */
+ /* MyRGMII5 -> RGMII5_RD1 */
{
- PIN_PRG1_PRU1_GPO1, PIN_MODE(4) | \
+ PIN_RGMII5_RD1, PIN_MODE(0) | \
((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
},
- /* MyRGMII2 -> RGMII2_RD2 -> AF23 */
+ /* MyRGMII5 -> RGMII5_RD2 */
{
- PIN_PRG1_PRU1_GPO2, PIN_MODE(4) | \
+ PIN_RGMII5_RD2, PIN_MODE(0) | \
((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
},
- /* MyRGMII2 -> RGMII2_RD3 -> AD23 */
+ /* MyRGMII5 -> RGMII5_RD3 */
{
- PIN_PRG1_PRU1_GPO3, PIN_MODE(4) | \
+ PIN_RGMII5_RD3, PIN_MODE(0) | \
((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
},
- /* MyRGMII2 -> RGMII2_RXC -> AE23 */
+ /* MyRGMII5 -> RGMII5_RXC */
{
- PIN_PRG1_PRU1_GPO6, PIN_MODE(4) | \
+ PIN_RGMII5_RXC, PIN_MODE(0) | \
((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
},
- /* MyRGMII2 -> RGMII2_RX_CTL -> AH24 */
+ /* MyRGMII5 -> RGMII5_RX_CTL */
{
- PIN_PRG1_PRU1_GPO4, PIN_MODE(4) | \
+ PIN_RGMII5_RX_CTL, PIN_MODE(0) | \
((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
},
- /* MyRGMII2 -> RGMII2_TD0 -> AJ25 */
+ /* MyRGMII5 -> RGMII5_TD0 */
{
- PIN_PRG1_PRU1_GPO11, PIN_MODE(4) | \
+ PIN_RGMII5_TD0, PIN_MODE(0) | \
((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))
},
- /* MyRGMII2 -> RGMII2_TD1 -> AH25 */
+ /* MyRGMII5 -> RGMII5_TD1 */
{
- PIN_PRG1_PRU1_GPO12, PIN_MODE(4) | \
+ PIN_RGMII5_TD1, PIN_MODE(0) | \
((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))
},
- /* MyRGMII2 -> RGMII2_TD2 -> AG25 */
+ /* MyRGMII5 -> RGMII5_TD2 */
{
- PIN_PRG1_PRU1_GPO13, PIN_MODE(4) | \
+ PIN_RGMII5_TD2, PIN_MODE(0) | \
((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))
},
- /* MyRGMII2 -> RGMII2_TD3 -> AH26 */
+ /* MyRGMII5 -> RGMII5_TD3 */
{
- PIN_PRG1_PRU1_GPO14, PIN_MODE(4) | \
+ PIN_RGMII5_TD3, PIN_MODE(0) | \
((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))
},
- /* MyRGMII2 -> RGMII2_TXC -> AJ26 */
+ /* MyRGMII5 -> RGMII5_TXC */
{
- PIN_PRG1_PRU1_GPO16, PIN_MODE(4) | \
- ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
+ PIN_RGMII5_TXC, PIN_MODE(0) | \
+ ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))
},
- /* MyRGMII2 -> RGMII2_TX_CTL -> AJ27 */
+ /* MyRGMII5 -> RGMII5_TX_CTL */
{
- PIN_PRG1_PRU1_GPO15, PIN_MODE(4) | \
- ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
+ PIN_RGMII5_TX_CTL, PIN_MODE(0) | \
+ ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))
},
{PINMUX_END}
};
@@ -476,7 +558,8 @@ static pinmuxModuleCfg_t gRgmiiPinCfg[] =
{3, TRUE, gRgmii3PinCfg},
{4, TRUE, gRgmii4PinCfg},
{1, TRUE, gRgmii1PinCfg},
- {2, TRUE, gRgmii2PinCfg},
+ {5, TRUE, gRgmii5PinCfg},
+ // {2, TRUE, gRgmii2PinCfg},
{PINMUX_END}
};
diff --git a/packages/ti/board/src/j721e_evm/board_ethernet_config.c b/packages/ti/board/src/j721e_evm/board_ethernet_config.c
index 575b2e2..35584b6 100755
--- a/packages/ti/board/src/j721e_evm/board_ethernet_config.c
+++ b/packages/ti/board/src/j721e_evm/board_ethernet_config.c
@@ -704,28 +704,32 @@ Board_STATUS Board_ethConfigCpsw9g(void)
uint8_t portNum;
/* On J721E EVM to use all 8 ports simultaneously, we use below configuration
- RGMII Ports - 1,3,4,8. QSGMII ports - 2 (main),5,6,7 (sub)*/
+ //RGMII Ports - 1,3,4,8. QSGMII ports - 2 (main),5,6,7 (sub)
+ RGMII Ports - 1,3,4,5. QSGMII ports - 2 (main),6,7,8 (sub)*/
+
/* Configures the CPSW9G RGMII ports */
for(portNum=0; portNum < BOARD_CPSW9G_PORT_MAX; portNum++)
{
- if ( 0U == portNum ||
- 2U == portNum ||
+ // if ( 0U == portNum ||
+ if ( 2U == portNum ||
3U == portNum ||
- 7U == portNum )
+ 4U == portNum )
{
status = Board_cpsw9gEthConfig(portNum, RGMII);
+ // status = Board_cpsw9gEthConfig(portNum, RMII);
}
else
{
- if (1U == portNum)
- {
- status = Board_cpsw9gEthConfig(portNum, QSGMII);
- }
- else
- {
- status = Board_cpsw9gEthConfig(portNum, QSGMII_SUB);
- }
+ status = Board_cpsw9gEthConfig(portNum, SGMII);
+ // if (1U == portNum)
+ // {
+ // status = Board_cpsw9gEthConfig(portNum, QSGMII);
+ // }
+ // else
+ // {
+ // status = Board_cpsw9gEthConfig(portNum, QSGMII_SUB);
+ // }
}
if(status != BOARD_SOK)
diff --git a/packages/ti/drv/enet/enet_component.mk b/packages/ti/drv/enet/enet_component.mk
index 82a75e7..2e51a04 100644
--- a/packages/ti/drv/enet/enet_component.mk
+++ b/packages/ti/drv/enet/enet_component.mk
@@ -302,12 +302,12 @@ endif
# 4 - Debug
# 5 - Verbose
ifeq ($(BUILD_PROFILE),debug)
- ENET_CFLAGS += -DENET_CFG_TRACE_LEVEL=4
+ ENET_CFLAGS += -DENET_CFG_TRACE_LEVEL=5
ENET_CFLAGS += -DENET_CFG_DEV_ERROR=1
ENET_CFLAGS += -DENETDMA_INSTRUMENTATION_ENABLED
ENET_CFLAGS += -DENETCPTS_INSTRUMENTATION_ENABLED
else
- ENET_CFLAGS += -DENET_CFG_TRACE_LEVEL=3
+ ENET_CFLAGS += -DENET_CFG_TRACE_LEVEL=5
endif
ifeq ($(SOC),$(filter $(SOC), am65xx))
diff --git a/packages/ti/drv/enet/examples/utils/V1/enet_appboardutils_j721e_evm.c b/packages/ti/drv/enet/examples/utils/V1/enet_appboardutils_j721e_evm.c
index 387b467..b461f63 100644
--- a/packages/ti/drv/enet/examples/utils/V1/enet_appboardutils_j721e_evm.c
+++ b/packages/ti/drv/enet/examples/utils/V1/enet_appboardutils_j721e_evm.c
@@ -266,11 +266,13 @@ void EnetBoard_initEthFw(void)
EnetBoard_configTorrentClks();
#endif
- if (Board_detectBoard(BOARD_ID_ENET))
- {
- status = Board_serdesCfgQsgmii();
- EnetAppUtils_assert(status == BOARD_SOK);
- }
+ // if (Board_detectBoard(BOARD_ID_ENET))
+ // {
+ // status = Board_serdesCfgQsgmii();
+ // EnetAppUtils_assert(status == BOARD_SOK);
+ // }
+ status = Board_serdesCfgSgmii();
+ EnetAppUtils_assert(status == BOARD_SOK);
#endif
}
@@ -351,8 +353,10 @@ uint32_t EnetBoard_getPhyAddr(Enet_Type enetType,
break;
case ENET_MAC_PORT_5:
- /* QSGMII port */
- phyAddr = 17U;
+ // /* QSGMII port */
+ // phyAddr = 17U;
+ /* RGMII port */
+ phyAddr = 0U;
break;
case ENET_MAC_PORT_6:
@@ -534,8 +538,10 @@ void EnetBoard_setPhyConfigRgmii(Enet_Type enetType,
(portNum == ENET_MAC_PORT_2) ||
(portNum == ENET_MAC_PORT_3) ||
(portNum == ENET_MAC_PORT_4) ||
+ (portNum == ENET_MAC_PORT_5) ||
(portNum == ENET_MAC_PORT_7) ||
(portNum == ENET_MAC_PORT_8));
+ EnetBoard_setEnetControl(enetType, 0U/* instId */, portNum, RGMII);
#elif defined (SOC_J7200)
if (enetType == ENET_CPSW_2G)
{
@@ -555,6 +561,7 @@ void EnetBoard_setPhyConfigRgmii(Enet_Type enetType,
phyCfg->phyAddr = 0U;
#else
phyCfg->phyAddr = EnetBoard_getPhyAddr(enetType, portNum);
+ printf("[LXC] phyCfg->phyAddr = %d, portNum = %d\n", phyCfg->phyAddr, portNum);
#endif
/* DP83867 specific configuration */
@@ -626,6 +633,7 @@ void EnetBoard_setPhyConfig(Enet_Type enetType,
if ( ENET_MAC_PORT_1 == portNum ||
ENET_MAC_PORT_3 == portNum ||
ENET_MAC_PORT_4 == portNum ||
+ ENET_MAC_PORT_5 == portNum ||
ENET_MAC_PORT_8 == portNum )
{
EnetBoard_setPhyConfigRgmii(enetType,
diff --git a/packages/ti/drv/enet/examples/utils/V1/enet_board_pinmux.c b/packages/ti/drv/enet/examples/utils/V1/enet_board_pinmux.c
index 0070c2b..726c756 100644
--- a/packages/ti/drv/enet/examples/utils/V1/enet_board_pinmux.c
+++ b/packages/ti/drv/enet/examples/utils/V1/enet_board_pinmux.c
@@ -86,7 +86,8 @@ int32_t EnetBoard_configEthFwPinmux (void)
/* Overwrite the ICSSG RGMII muc configurations with CPSW */
/* Below is CPSW9G QSGMII pinmux configuration,
RGMII Ports - 1,3,4,8. QSGMII ports - 2,5,6,7 */
- Board_pinmuxUpdate(gJ721E_MainPinmuxDataGesiCpsw9gQsgmii,
+ // Board_pinmuxUpdate(gJ721E_MainPinmuxDataGesiCpsw9gQsgmii,
+ Board_pinmuxUpdate(gJ721E_MainPinmuxDataGesiCpsw9g,
BOARD_SOC_DOMAIN_MAIN);
#elif defined(BUILD_MCU2_0) && defined(SOC_J7200)
/* Below is CPSW5G QSGMII pinmux configuration,
diff --git a/packages/ti/drv/enet/examples/utils/V1/enet_board_pinmux_j721e_data.c b/packages/ti/drv/enet/examples/utils/V1/enet_board_pinmux_j721e_data.c
index f4d2f90..0497db6 100644
--- a/packages/ti/drv/enet/examples/utils/V1/enet_board_pinmux_j721e_data.c
+++ b/packages/ti/drv/enet/examples/utils/V1/enet_board_pinmux_j721e_data.c
@@ -209,6 +209,8 @@ static pinmuxPerCfg_t gGpio2PinCfg_phyReset[] =
PIN_RGMII5_RD0, PIN_MODE(7) | \
((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
},
+
+ /* TODO: 配置复位引脚 */
{PINMUX_END}
};
diff --git a/packages/ti/drv/enet/examples/utils/enet_board_j7xevm.c b/packages/ti/drv/enet/examples/utils/enet_board_j7xevm.c
index b186c0a..f02371b 100644
--- a/packages/ti/drv/enet/examples/utils/enet_board_j7xevm.c
+++ b/packages/ti/drv/enet/examples/utils/enet_board_j7xevm.c
@@ -1313,10 +1313,11 @@ void EnetBoard_getMacAddrList(uint8_t macAddr[][ENET_MAC_ADDR_LEN],
* addresses in Linux builds. For RTOS build, MAC addresses will still
* be read from EEPROM as such I2C contention isn't an problem.
*/
+ // set static macaddr
uint8_t macAddrBuf[][ENET_MAC_ADDR_LEN] =
{
- { 0x70U, 0xFFU, 0x76U, 0x1DU, 0x92U, 0xC1U },
{ 0x70U, 0xFFU, 0x76U, 0x1DU, 0x92U, 0xC2U },
+ { 0x70U, 0xFFU, 0x76U, 0x1DU, 0x92U, 0xC1U },
{ 0x70U, 0xFFU, 0x76U, 0x1DU, 0x92U, 0xC3U },
{ 0x70U, 0xFFU, 0x76U, 0x1DU, 0x92U, 0xC4U },
{ 0x70U, 0xFFU, 0x76U, 0x1DU, 0x92U, 0xC5U },
diff --git a/packages/ti/drv/enet/src/mod/mdio.c b/packages/ti/drv/enet/src/mod/mdio.c
index fbdcead..79f0bc9 100644
--- a/packages/ti/drv/enet/src/mod/mdio.c
+++ b/packages/ti/drv/enet/src/mod/mdio.c
@@ -155,7 +155,8 @@ void Mdio_initCfg(Mdio_Cfg *mdioCfg)
mdioCfg->mdioBusFreqHz = MDIO_MDIOBUS_DFLT_FREQ_HZ;
mdioCfg->phyStatePollFreqHz = mdioCfg->mdioBusFreqHz;
mdioCfg->pollEnMask = ENET_MDIO_PHY_ADDR_MASK_ALL;
- mdioCfg->c45EnMask = ENET_MDIO_PHY_ADDR_MASK_NONE;
+ // mdioCfg->c45EnMask = ENET_MDIO_PHY_ADDR_MASK_NONE;
+ mdioCfg->c45EnMask = ENET_MDIO_PHY_ADDR_MASK_ALL;
mdioCfg->isMaster = true;
}
diff --git a/packages/ti/drv/enet/src/per/cpsw.c b/packages/ti/drv/enet/src/per/cpsw.c
index 18b0872..af1c048 100644
--- a/packages/ti/drv/enet/src/per/cpsw.c
+++ b/packages/ti/drv/enet/src/per/cpsw.c
@@ -650,6 +650,7 @@ void Cpsw_periodicTick(EnetPer_Handle hPer)
if (hPhy != NULL)
{
/* Run PHY tick */
+ // ENETTRACE_ERR("[LXC]: Cpsw_periodicTick 222222 \n");
linkStatus = EnetPhy_tick(hPhy);
/* Handle link up/down events */
diff --git a/packages/ti/drv/enet/src/per/cpsw_tpr12.c b/packages/ti/drv/enet/src/per/cpsw_tpr12.c
index 3080ccf..6bb643d 100644
--- a/packages/ti/drv/enet/src/per/cpsw_tpr12.c
+++ b/packages/ti/drv/enet/src/per/cpsw_tpr12.c
@@ -625,6 +625,7 @@ void Cpsw_periodicTick(EnetPer_Handle hPer)
if (hPhy != NULL)
{
/* Run PHY tick */
+ // ENETTRACE_ERR("[LXC]: Cpsw_periodicTick tpr12 1111\n");
linkStatus = EnetPhy_tick(hPhy);
/* Handle link up/down events */
diff --git a/packages/ti/drv/enet/src/per/icssg.c b/packages/ti/drv/enet/src/per/icssg.c
index 2d1247f..4ad3d3a 100644
--- a/packages/ti/drv/enet/src/per/icssg.c
+++ b/packages/ti/drv/enet/src/per/icssg.c
@@ -1754,6 +1754,8 @@ void Icssg_periodicTick(EnetPer_Handle hPer)
//EnetOsal_lockMutex(hIcssg->lock);
/* Run PHY tick */
+ ENETTRACE_ERR("[LXC]: Icssg_periodicTick 333333333 \n");
+
linkStatus = EnetPhy_tick(hPhy);
/* Handle link up/down events */
diff --git a/packages/ti/drv/enet/src/phy/enetphy.c b/packages/ti/drv/enet/src/phy/enetphy.c
index 43a70bc..5ac6b11 100644
--- a/packages/ti/drv/enet/src/phy/enetphy.c
+++ b/packages/ti/drv/enet/src/phy/enetphy.c
@@ -118,8 +118,6 @@ static void EnetPhy_defaultState(EnetPhy_Handle hPhy);
static void EnetPhy_findingState(EnetPhy_Handle hPhy);
-static void EnetPhy_findingState(EnetPhy_Handle hPhy);
-
static void EnetPhy_foundState(EnetPhy_Handle hPhy);
static void EnetPhy_resetWaitState(EnetPhy_Handle hPhy);
@@ -363,6 +361,7 @@ void EnetPhy_close(EnetPhy_Handle hPhy)
EnetPhy_releaseHandle(hPhy);
}
+extern void ACD_test(EnetPhy_Handle hPhy);
EnetPhy_LinkStatus EnetPhy_tick(EnetPhy_Handle hPhy)
{
EnetPhy_State *state = &hPhy->state;
@@ -370,6 +369,15 @@ EnetPhy_LinkStatus EnetPhy_tick(EnetPhy_Handle hPhy)
EnetPhy_FsmState currFsmState;
EnetPhy_LinkStatus status;
+ // static int x_count = 1;
+
+ // printf("EnetPhy_tick test ^^^^^ i=0x%x, addr=%x, state->fsmState= %d\n", x_count, hPhy->addr, state->fsmState);
+ // if (x_count % 100 == 0) {
+ // ACD_test(hPhy);
+ // }
+ // if (x_count < 0xffffffff)
+ // x_count++;
+
/* TODO: Check if pending state transitions needs to be applied,
* i.e. from EnetPhy_setPhyMode() */
@@ -514,7 +522,8 @@ bool EnetPhy_isAlive(EnetPhy_Handle hPhy)
else
{
/* Alternatively, read BMSR - PHY is alive if transaction is successful */
- status = hMdio->readC22(phyGroup, phyAddr, PHY_BMSR, &val, hPhy->mdioArgs);
+ // status = hMdio->readC22(phyGroup, phyAddr, PHY_BMSR, &val, hPhy->mdioArgs);
+ status = hMdio->readC45(phyGroup, phyAddr, 1, PHY_BMSR, &val, hPhy->mdioArgs);
ENETTRACE_ERR_IF(status != ENETPHY_SOK,
"PHY %u: Failed to read reg %u: %d\n", phyAddr, PHY_BMSR, status);
if (status == ENETPHY_SOK)
@@ -601,6 +610,7 @@ int32_t EnetPhy_getLinkCfg(EnetPhy_Handle hPhy,
return status;
}
+extern int g_DEVAD;
int32_t EnetPhy_readReg(EnetPhy_Handle hPhy,
uint32_t reg,
uint16_t *val)
@@ -610,12 +620,17 @@ int32_t EnetPhy_readReg(EnetPhy_Handle hPhy,
uint32_t phyAddr = hPhy->addr;
int32_t status;
- status = hMdio->readC22(phyGroup, phyAddr, reg, val, hPhy->mdioArgs);
+ // printf("[LXC]: EnetPhy_readReg . phyAddr = %d\n", phyAddr);
+
+ // status = hMdio->readC22(phyGroup, phyAddr, reg, val, hPhy->mdioArgs);
+ status = hMdio->readC45(phyGroup, phyAddr, g_DEVAD, reg, val, hPhy->mdioArgs);
ENETTRACE_ERR_IF(status != ENETPHY_SOK,
"PHY %u: Failed to read reg %u: %d\n", phyAddr, reg, status);
ENETTRACE_VERBOSE_IF(status == ENETPHY_SOK,
"PHY %u: reg %u val 0x%04x %s\n", phyAddr, reg, *val);
+ // printf("[LXC]: EnetPhy_readReg . status = %d\n", status);
+
return status;
}
@@ -628,7 +643,8 @@ int32_t EnetPhy_writeReg(EnetPhy_Handle hPhy,
uint32_t phyAddr = hPhy->addr;
int32_t status;
- status = hMdio->writeC22(phyGroup, phyAddr, reg, val, hPhy->mdioArgs);
+ // status = hMdio->writeC22(phyGroup, phyAddr, reg, val, hPhy->mdioArgs);
+ status = hMdio->writeC45(phyGroup, phyAddr, g_DEVAD, reg, val, hPhy->mdioArgs);
ENETTRACE_ERR_IF(status != ENETPHY_SOK,
"PHY %u: Failed to write reg %u: %d\n", phyAddr, reg, status);
ENETTRACE_VERBOSE_IF(status == ENETPHY_SOK,
@@ -648,7 +664,8 @@ int32_t EnetPhy_rmwReg(EnetPhy_Handle hPhy,
int32_t status;
uint16_t data = 0U;
- status = hMdio->readC22(phyGroup, phyAddr, reg, &data, hPhy->mdioArgs);
+ // status = hMdio->readC22(phyGroup, phyAddr, reg, &data, hPhy->mdioArgs);
+ status = hMdio->readC45(phyGroup, phyAddr, g_DEVAD, reg, &data, hPhy->mdioArgs);
ENETTRACE_ERR_IF(status != ENETPHY_SOK,
"PHY %u: Failed to read reg %u: %d\n", phyAddr, reg, status);
ENETTRACE_VERBOSE_IF(status == ENETPHY_SOK,
@@ -658,7 +675,8 @@ int32_t EnetPhy_rmwReg(EnetPhy_Handle hPhy,
{
data = (data & ~mask) | (val & mask);
- status = hMdio->writeC22(phyGroup, phyAddr, reg, data, hPhy->mdioArgs);
+ // status = hMdio->writeC22(phyGroup, phyAddr, reg, data, hPhy->mdioArgs);
+ status = hMdio->writeC45(phyGroup, phyAddr, 1, reg, data, hPhy->mdioArgs);
ENETTRACE_ERR_IF(status != ENETPHY_SOK,
"PHY %u: Failed to write reg %u: %d\n", phyAddr, reg, status);
ENETTRACE_VERBOSE_IF(status == ENETPHY_SOK,
@@ -1074,7 +1092,7 @@ static void EnetPhy_enableState(EnetPhy_Handle hPhy)
{
/* Set PHY in normal mode */
ENETTRACE_DBG("PHY %u: enable\n", hPhy->addr);
- EnetPhy_rmwReg(hPhy, PHY_BMCR, BMCR_ISOLATE | BMCR_PWRDOWN, 0U);
+ // EnetPhy_rmwReg(hPhy, PHY_BMCR, BMCR_ISOLATE | BMCR_PWRDOWN, 0U);
/* PHY-specific 'extended' configuration */
if ((hPhy->hDrv->config != NULL) &&
@@ -1198,11 +1216,11 @@ static void EnetPhy_setupNway(EnetPhy_Handle hPhy)
nway1000Advertise |= GIGCR_1000HD;
}
- EnetPhy_rmwReg(hPhy, PHY_ANAR, ANAR_100 | ANAR_10, nwayAdvertise);
+ // EnetPhy_rmwReg(hPhy, PHY_ANAR, ANAR_100 | ANAR_10, nwayAdvertise);
if ((state->phyLinkCaps & ENETPHY_LINK_CAP_1000) != 0U)
{
- EnetPhy_rmwReg(hPhy, PHY_GIGCR, GIGCR_1000, nway1000Advertise);
+ ;// EnetPhy_rmwReg(hPhy, PHY_GIGCR, GIGCR_1000, nway1000Advertise);
}
state->needsNwayCfg = false;
@@ -1210,12 +1228,12 @@ static void EnetPhy_setupNway(EnetPhy_Handle hPhy)
/* Restart auto-negotiation */
ENETTRACE_DBG("PHY %u: restart autonegotiation\n", hPhy->addr);
- EnetPhy_rmwReg(hPhy, PHY_BMCR, BMCR_ANEN, BMCR_ANEN);
+ // EnetPhy_rmwReg(hPhy, PHY_BMCR, BMCR_ANEN, BMCR_ANEN);
/* TODO: is MII_ENETPHY_FD needed for auto-negotiation? */
- EnetPhy_rmwReg(hPhy, PHY_BMCR,
- BMCR_ANRESTART | BMCR_FD,
- BMCR_ANRESTART | BMCR_FD);
+ // EnetPhy_rmwReg(hPhy, PHY_BMCR,
+ // BMCR_ANRESTART | BMCR_FD,
+ // BMCR_ANRESTART | BMCR_FD);
}
static void EnetPhy_setupManual(EnetPhy_Handle hPhy,
@@ -1292,16 +1310,27 @@ static void EnetPhy_setupManual(EnetPhy_Handle hPhy,
hPhy->addr, EnetPhy_getModeString(state->speed, state->duplexity));
}
+extern int g_DEVAD;
static void EnetPhy_loopbackState(EnetPhy_Handle hPhy)
{
bool loopback = false;
int32_t status;
- uint16_t val;
+ // uint16_t val;
+ uint16_t val1, val2;
+
+ g_DEVAD = 0x03;
+ status = EnetPhy_readReg(hPhy, 0x0000, &val1);
+ g_DEVAD = 0x01;
+ status = EnetPhy_readReg(hPhy, 0x0000, &val2);
- status = EnetPhy_readReg(hPhy, PHY_BMCR, &val);
+ // status = EnetPhy_readReg(hPhy, PHY_BMCR, &val);
if (status == ENETPHY_SOK)
{
- loopback = ((val & BMCR_LOOPBACK) != 0U);
+ // loopback = ((val & BMCR_LOOPBACK) != 0U);
+ if (val2 & 0x1 != 0 || val1 & 0x4000 != 0) {
+ EnetUtils_printf("[xujibin] %s:%d lookback true\n", __FUNCTION__, __LINE__);
+ loopback = true;
+ }
}
else
{
@@ -1325,6 +1354,7 @@ static void EnetPhy_nwayStartState(EnetPhy_Handle hPhy)
/* Wait for NWAY to start */
EnetPhy_readReg(hPhy, PHY_BMCR, &mode);
+ mode |= BMCR_ANRESTART;
if ((mode & BMCR_ANRESTART) == 0U)
{
@@ -1355,6 +1385,8 @@ static void EnetPhy_nwayWaitState(EnetPhy_Handle hPhy)
"PHY %u: unexpected state for strapped PHY\n", hPhy->addr);
EnetPhy_readReg(hPhy, PHY_BMSR, &status);
+ status |= BMSR_ANCOMPLETE;
+ status |= BMSR_LINKSTS;
if (0U != (status & BMSR_ANCOMPLETE))
{
nwayCaps = EnetPhy_findCommonNwayCaps(hPhy);
@@ -1396,6 +1428,7 @@ static void EnetPhy_linkWaitState(EnetPhy_Handle hPhy)
EnetPhy_readReg(hPhy, PHY_BMSR, &status);
+ status |= BMSR_LINKSTS;
if ((status & BMSR_LINKSTS) != 0U)
{
/* Populate FSM state now as most FSM states are bypassed for strapped PHYs */
@@ -1450,59 +1483,77 @@ static void EnetPhy_linkedState(EnetPhy_Handle hPhy)
static bool EnetPhy_isNwayCapable(EnetPhy_Handle hPhy)
{
- uint16_t val = 0U;
+ // uint16_t val = 0U;
/* Get the PHY Status */
- EnetPhy_readReg(hPhy, PHY_BMSR, &val);
+ // EnetPhy_readReg(hPhy, PHY_BMSR, &val);
- return ((val & BMSR_ANCAPABLE) != 0U);
+ // return ((val & BMSR_ANCAPABLE) != 0U);
+ return true;
}
+extern int g_speed;
static uint32_t EnetPhy_getLocalCaps(EnetPhy_Handle hPhy)
{
uint32_t caps = 0U;
- uint16_t val = 0U;
- /* Get 10/100 Mbps capabilities */
- EnetPhy_readReg(hPhy, PHY_BMSR, &val);
- if ((val & BMSR_100FD) != 0U)
- {
- caps |= ENETPHY_LINK_CAP_FD100;
- }
-
- if ((val & BMSR_100HD) != 0U)
- {
- caps |= ENETPHY_LINK_CAP_HD100;
- }
-
- if ((val & BMSR_10FD) != 0U)
- {
- caps |= ENETPHY_LINK_CAP_FD10;
- }
-
- if ((val & BMSR_10HD) != 0U)
- {
- caps |= ENETPHY_LINK_CAP_HD10;
- }
-
- /* Get extended (1 Gbps) capabilities if supported */
- if ((val & BMSR_GIGEXTSTS) != 0U)
- {
- EnetPhy_readReg(hPhy, PHY_GIGESR, &val);
-
- if ((val & GIGESR_1000FD) != 0U)
- {
- caps |= ENETPHY_LINK_CAP_FD1000;
- }
-
- if ((val & GIGESR_1000HD) != 0U)
- {
- caps |= ENETPHY_LINK_CAP_HD1000;
- }
+ /* Get 10/100/1000 Mbps capabilities */
+ caps |= ENETPHY_LINK_CAP_FD100;
+ caps |= ENETPHY_LINK_CAP_HD100;
+ caps |= ENETPHY_LINK_CAP_FD10;
+ caps |= ENETPHY_LINK_CAP_HD10;
+ if (g_speed == 1000) {
+ caps |= ENETPHY_LINK_CAP_FD1000;
+ caps |= ENETPHY_LINK_CAP_HD1000;
}
return caps;
}
+// static uint32_t EnetPhy_getLocalCaps(EnetPhy_Handle hPhy)
+// {
+// uint32_t caps = 0U;
+// // uint16_t val = 0U;
+
+// /* Get 10/100 Mbps capabilities */
+// EnetPhy_readReg(hPhy, PHY_BMSR, &val);
+// if ((val & BMSR_100FD) != 0U)
+// {
+// caps |= ENETPHY_LINK_CAP_FD100;
+// }
+
+// if ((val & BMSR_100HD) != 0U)
+// {
+// caps |= ENETPHY_LINK_CAP_HD100;
+// }
+
+// if ((val & BMSR_10FD) != 0U)
+// {
+// caps |= ENETPHY_LINK_CAP_FD10;
+// }
+
+// if ((val & BMSR_10HD) != 0U)
+// {
+// caps |= ENETPHY_LINK_CAP_HD10;
+// }
+
+// /* Get extended (1 Gbps) capabilities if supported */
+// if ((val & BMSR_GIGEXTSTS) != 0U)
+// {
+// EnetPhy_readReg(hPhy, PHY_GIGESR, &val);
+
+// if ((val & GIGESR_1000FD) != 0U)
+// {
+// caps |= ENETPHY_LINK_CAP_FD1000;
+// }
+
+// if ((val & GIGESR_1000HD) != 0U)
+// {
+// caps |= ENETPHY_LINK_CAP_HD1000;
+// }
+// }
+
+// return caps;
+// }
static uint32_t EnetPhy_findCommonCaps(EnetPhy_Handle hPhy)
{
@@ -1513,49 +1564,58 @@ static uint32_t EnetPhy_findCommonCaps(EnetPhy_Handle hPhy)
/* Get local device capabilities */
EnetPhy_readReg(hPhy, PHY_ANAR, &val);
- if ((val & ANAR_100FD) != 0U)
- {
- localCaps |= ENETPHY_LINK_CAP_FD100;
- }
+ // if ((val & ANAR_100FD) != 0U)
+ // {
+ // localCaps |= ENETPHY_LINK_CAP_FD100;
+ // }
- if ((val & ANAR_100HD) != 0U)
- {
- localCaps |= ENETPHY_LINK_CAP_HD100;
- }
+ // if ((val & ANAR_100HD) != 0U)
+ // {
+ // localCaps |= ENETPHY_LINK_CAP_HD100;
+ // }
- if ((val & ANAR_10FD) != 0U)
- {
- localCaps |= ENETPHY_LINK_CAP_FD10;
- }
+ // if ((val & ANAR_10FD) != 0U)
+ // {
+ // localCaps |= ENETPHY_LINK_CAP_FD10;
+ // }
- if ((val & ANAR_10HD) != 0U)
- {
- localCaps |= ENETPHY_LINK_CAP_HD10;
- }
+ // if ((val & ANAR_10HD) != 0U)
+ // {
+ // localCaps |= ENETPHY_LINK_CAP_HD10;
+ // }
+
+ localCaps |= ENETPHY_LINK_CAP_FD100;
+ localCaps |= ENETPHY_LINK_CAP_HD100;
+ localCaps |= ENETPHY_LINK_CAP_FD10;
+ localCaps |= ENETPHY_LINK_CAP_HD10;
/* Get link partner capabilities */
val = 0U;
EnetPhy_readReg(hPhy, PHY_ANLPAR, &val);
- if ((val & ANLPAR_100FD) != 0U)
- {
- partnerCaps |= ENETPHY_LINK_CAP_FD100;
- }
-
- if ((val & ANLPAR_100HD) != 0U)
- {
- partnerCaps |= ENETPHY_LINK_CAP_HD100;
- }
-
- if ((val & ANLPAR_10FD) != 0U)
- {
- partnerCaps |= ENETPHY_LINK_CAP_FD10;
- }
-
- if ((val & ANLPAR_10HD) != 0U)
- {
- partnerCaps |= ENETPHY_LINK_CAP_HD10;
- }
+ // if ((val & ANLPAR_100FD) != 0U)
+ // {
+ // partnerCaps |= ENETPHY_LINK_CAP_FD100;
+ // }
+
+ // if ((val & ANLPAR_100HD) != 0U)
+ // {
+ // partnerCaps |= ENETPHY_LINK_CAP_HD100;
+ // }
+
+ // if ((val & ANLPAR_10FD) != 0U)
+ // {
+ // partnerCaps |= ENETPHY_LINK_CAP_FD10;
+ // }
+
+ // if ((val & ANLPAR_10HD) != 0U)
+ // {
+ // partnerCaps |= ENETPHY_LINK_CAP_HD10;
+ // }
+ partnerCaps |= ENETPHY_LINK_CAP_FD100;
+ partnerCaps |= ENETPHY_LINK_CAP_HD100;
+ partnerCaps |= ENETPHY_LINK_CAP_FD10;
+ partnerCaps |= ENETPHY_LINK_CAP_HD10;
ENETTRACE_DBG("PHY %u: local caps: %s\n",
hPhy->addr, EnetPhy_getCapsString(localCaps));
@@ -1571,41 +1631,47 @@ static uint32_t EnetPhy_findCommon1000Caps(EnetPhy_Handle hPhy)
{
uint32_t localCaps = 0U;
uint32_t partnerCaps = 0U;
- uint16_t val;
-
- /* Get local device capabilities */
- EnetPhy_readReg(hPhy, PHY_GIGCR, &val);
-
- if ((val & GIGCR_1000FD) != 0U)
- {
+ // uint16_t val;
+
+ // /* Get local device capabilities */
+ // EnetPhy_readReg(hPhy, PHY_GIGCR, &val);
+
+ // if ((val & GIGCR_1000FD) != 0U)
+ // {
+ // localCaps |= ENETPHY_LINK_CAP_FD1000;
+ // }
+
+ // if ((val & GIGCR_1000HD) != 0U)
+ // {
+ // localCaps |= ENETPHY_LINK_CAP_HD1000;
+ // }
+
+ // /* Get link partner capabilities */
+ // EnetPhy_readReg(hPhy, PHY_GIGSR, &val);
+
+ // if ((val & GIGSR_1000FD) != 0U)
+ // {
+ // partnerCaps |= ENETPHY_LINK_CAP_FD1000;
+ // }
+
+ // if ((val & GIGSR_1000FD) != 0U)
+ // {
+ // partnerCaps |= ENETPHY_LINK_CAP_HD1000;
+ // }
+
+ // ENETTRACE_DBG("PHY %u: local caps: %s\n",
+ // hPhy->addr, EnetPhy_getCapsString(localCaps));
+ // ENETTRACE_DBG("PHY %u: partner caps: %s\n",
+ // hPhy->addr, EnetPhy_getCapsString(partnerCaps));
+ // ENETTRACE_DBG("PHY %u: common caps: %s\n",
+ // hPhy->addr, EnetPhy_getCapsString(localCaps & partnerCaps));
+
+ if (g_speed == 1000) {
localCaps |= ENETPHY_LINK_CAP_FD1000;
- }
-
- if ((val & GIGCR_1000HD) != 0U)
- {
localCaps |= ENETPHY_LINK_CAP_HD1000;
- }
-
- /* Get link partner capabilities */
- EnetPhy_readReg(hPhy, PHY_GIGSR, &val);
-
- if ((val & GIGSR_1000FD) != 0U)
- {
partnerCaps |= ENETPHY_LINK_CAP_FD1000;
- }
-
- if ((val & GIGSR_1000FD) != 0U)
- {
partnerCaps |= ENETPHY_LINK_CAP_HD1000;
}
-
- ENETTRACE_DBG("PHY %u: local caps: %s\n",
- hPhy->addr, EnetPhy_getCapsString(localCaps));
- ENETTRACE_DBG("PHY %u: partner caps: %s\n",
- hPhy->addr, EnetPhy_getCapsString(partnerCaps));
- ENETTRACE_DBG("PHY %u: common caps: %s\n",
- hPhy->addr, EnetPhy_getCapsString(localCaps & partnerCaps));
-
return (localCaps & partnerCaps);
}
@@ -1640,6 +1706,7 @@ static uint32_t EnetPhy_findCommonNwayCaps(EnetPhy_Handle hPhy)
return nwayCaps;
}
+extern int g_loopback;
static bool EnetPhy_isPhyLinked(EnetPhy_Handle hPhy)
{
EnetPhy_MdioHandle hMdio = hPhy->hMdio;
@@ -1649,6 +1716,9 @@ static bool EnetPhy_isPhyLinked(EnetPhy_Handle hPhy)
uint16_t val = 0U;
int32_t status;
+ if (g_loopback == 1)
+ return true;
+
/* Get PHY link status */
if (hMdio->isLinked != NULL)
{
@@ -1660,7 +1730,8 @@ static bool EnetPhy_isPhyLinked(EnetPhy_Handle hPhy)
else
{
/* Alternatively, BMSR[2] Link Status bit can be checked */
- status = hMdio->readC22(phyGroup, phyAddr, PHY_BMSR, &val, hPhy->mdioArgs);
+ // status = hMdio->readC22(phyGroup, phyAddr, PHY_BMSR, &val, hPhy->mdioArgs);
+ status = hMdio->readC45(phyGroup, phyAddr, 1, PHY_BMSR, &val, hPhy->mdioArgs);
ENETTRACE_ERR_IF(status != ENETPHY_SOK,
"PHY %u: Failed to read reg %u: %d\n", phyAddr, PHY_BMSR, status);
if ((status == ENETPHY_SOK) &&
diff --git a/packages/ti/drv/enet/src/phy/generic_phy.c b/packages/ti/drv/enet/src/phy/generic_phy.c
index 21200cb..1d3534c 100644
--- a/packages/ti/drv/enet/src/phy/generic_phy.c
+++ b/packages/ti/drv/enet/src/phy/generic_phy.c
@@ -50,6 +50,9 @@
#include "enetphy_priv.h"
#include "generic_phy.h"
+#include <ti/drv/i2c/I2C.h>
+#include <stdio.h>
+
/* ========================================================================== */
/* Macros & Typedefs */
/* ========================================================================== */
@@ -72,6 +75,8 @@ static bool GenericPhy_isPhyDevSupported(EnetPhy_Handle hPhy,
static bool GenericPhy_isMacModeSupported(EnetPhy_Handle hPhy,
EnetPhy_Mii mii);
+static void Bcm89881_config(EnetPhy_Handle hPhy);
+
/* ========================================================================== */
/* Global Variables */
/* ========================================================================== */
@@ -92,6 +97,88 @@ EnetPhy_Drv gEnetPhyDrvGeneric =
/* ========================================================================== */
/* Function Definitions */
/* ========================================================================== */
+#define TCA6424_CMD_AUTO_INC ((uint8_t) 0x80U)
+
+/* Input status register */
+#define TCA6424_REG_INPUT0 ((UInt8) 0x00U)
+#define TCA6424_REG_INPUT1 ((UInt8) 0x01U)
+#define TCA6424_REG_INPUT2 ((UInt8) 0x02U)
+
+/* Output register to change state of output BIT set to 1, output set HIGH */
+#define TCA6424_REG_OUTPUT0 ((uint8_t) 0x04U)
+#define TCA6424_REG_OUTPUT1 ((uint8_t) 0x05U)
+#define TCA6424_REG_OUTPUT2 ((uint8_t) 0x06U)
+
+/* Configuration register. BIT = '1' sets port to input, BIT = '0' sets
+ * port to output */
+#define TCA6424_REG_CONFIG0 ((uint8_t) 0x0CU)
+#define TCA6424_REG_CONFIG1 ((uint8_t) 0x0DU)
+#define TCA6424_REG_CONFIG2 ((uint8_t) 0x0EU)
+
+void SetupI2CTransfer(I2C_Handle handle, uint32_t slaveAddr,
+ uint8_t *writeData, uint32_t numWriteBytes,
+ uint8_t *readData, uint32_t numReadBytes)
+{
+ bool status;
+ I2C_Transaction i2cTransaction;
+
+ printf("\n[LXC]: SetupI2CTransfer start. \n");
+ I2C_transactionInit(&i2cTransaction);
+ i2cTransaction.slaveAddress = slaveAddr;
+ i2cTransaction.writeBuf = (uint8_t *)&writeData[0];
+ i2cTransaction.writeCount = numWriteBytes;
+ i2cTransaction.readBuf = (uint8_t *)&readData[0];
+ i2cTransaction.readCount = numReadBytes;
+ status = I2C_transfer(handle, &i2cTransaction);
+ if(FALSE == status)
+ {
+ printf("\n Data Transfer failed. \n");
+ }
+ printf("\n[LXC]: SetupI2CTransfer end. \n");
+}
+extern void Board_delay(uint32_t delayCycles);
+void Bcm89881_init(EnetPhy_Handle hPhy)
+{
+ I2C_Params i2cParams;
+ I2C_Handle handle = NULL;
+ uint8_t dataToSlave[4];
+
+ /*
+ * Configuring TCA6424 IO Exp 2 with addr 0x22
+ * This io expander is controlled by i2c0
+ */
+ /* I2C initialization */
+ printf("\n[LXC]: Bcm89881_init start. \n");
+ I2C_init();
+ I2C_Params_init(&i2cParams);
+ i2cParams.transferMode = I2C_MODE_BLOCKING;
+ i2cParams.bitRate = I2C_400kHz;
+ i2cParams.transferCallbackFxn = NULL;
+
+ handle = I2C_open(0U, &i2cParams);
+
+printf("\n[LXC]: Bcm89881_init ing 11111. \n");
+ dataToSlave[0] = TCA6424_REG_CONFIG0 | TCA6424_CMD_AUTO_INC;
+ dataToSlave[1] = 0x0U;
+ SetupI2CTransfer(handle, 0x22, &dataToSlave[0], 2, NULL, 0);
+printf("\n[LXC]: Bcm89881_init ing 22222. \n");
+
+ dataToSlave[0] = TCA6424_REG_INPUT0 | TCA6424_CMD_AUTO_INC;
+ dataToSlave[1] = 0x0U;
+ dataToSlave[2] = 0x0U;
+ dataToSlave[3] = 0x0U;
+ SetupI2CTransfer(handle, 0x22, &dataToSlave[0], 1, &dataToSlave[1], 3);
+printf("\n[LXC]: Bcm89881_init ing 33333. \n");
+
+ /* Set P20 to 0. Delay 22, and Set to 1;
+ */
+ Board_delay(22);
+ dataToSlave[0] = TCA6424_REG_OUTPUT2;
+ dataToSlave[1] |= 0x1;
+ SetupI2CTransfer(handle, 0x22, &dataToSlave[0], 1, &dataToSlave[1], 1);
+ printf("\n[LXC]: Bcm89881_init Stop. \n");
+
+}
static bool GenericPhy_isPhyDevSupported(EnetPhy_Handle hPhy,
const EnetPhy_Version *version)
@@ -112,7 +199,10 @@ void GenericPhy_reset(EnetPhy_Handle hPhy)
ENETTRACE_DBG("PHY %u: reset\n", hPhy->addr);
/* Reset the PHY */
- EnetPhy_rmwReg(hPhy, PHY_BMCR, BMCR_RESET, BMCR_RESET);
+ // EnetPhy_rmwReg(hPhy, PHY_BMCR, BMCR_RESET, BMCR_RESET);
+ printf("\n[LXC]: GenericPhy_reset. PHY %u: reset \n", hPhy->addr);
+
+ Bcm89881_config(hPhy);
}
bool GenericPhy_isResetComplete(EnetPhy_Handle hPhy)
@@ -137,65 +227,72 @@ int32_t GenericPhy_readExtReg(EnetPhy_Handle hPhy,
uint32_t reg,
uint16_t *val)
{
- uint16_t devad = MMD_CR_DEVADDR;
- int32_t status;
+ // uint16_t devad = MMD_CR_DEVADDR;
+ // int32_t status;
- status = EnetPhy_writeReg(hPhy, PHY_MMD_CR, devad | MMD_CR_ADDR);
+ // status = EnetPhy_writeReg(hPhy, PHY_MMD_CR, devad | MMD_CR_ADDR);
- if (status == ENETPHY_SOK)
- {
- status = EnetPhy_writeReg(hPhy, PHY_MMD_DR, reg);
- }
+ // if (status == ENETPHY_SOK)
+ // {
+ // status = EnetPhy_writeReg(hPhy, PHY_MMD_DR, reg);
+ // }
- if (status == ENETPHY_SOK)
- {
- EnetPhy_writeReg(hPhy, PHY_MMD_CR, devad | MMD_CR_DATA_NOPOSTINC);
- }
+ // if (status == ENETPHY_SOK)
+ // {
+ // EnetPhy_writeReg(hPhy, PHY_MMD_CR, devad | MMD_CR_DATA_NOPOSTINC);
+ // }
- if (status == ENETPHY_SOK)
- {
- status = EnetPhy_readReg(hPhy, PHY_MMD_DR, val);
- }
+ // if (status == ENETPHY_SOK)
+ // {
+ // status = EnetPhy_readReg(hPhy, PHY_MMD_DR, val);
+ // }
- ENETTRACE_VERBOSE_IF(status == ENETPHY_SOK,
- "PHY %u: failed to read reg %u\n", hPhy->addr, reg);
- ENETTRACE_ERR_IF(status != ENETPHY_SOK,
- "PHY %u: read reg %u val 0x%04x\n", hPhy->addr, reg, *val);
+ // ENETTRACE_VERBOSE_IF(status == ENETPHY_SOK,
+ // "PHY %u: failed to read reg %u\n", hPhy->addr, reg);
+ // ENETTRACE_ERR_IF(status != ENETPHY_SOK,
+ // "PHY %u: read reg %u val 0x%04x\n", hPhy->addr, reg, *val);
- return status;
+ // return status;
+ return ENETPHY_SOK;
}
int32_t GenericPhy_writeExtReg(EnetPhy_Handle hPhy,
uint32_t reg,
uint16_t val)
{
- uint16_t devad = MMD_CR_DEVADDR;
- int32_t status;
+ // uint16_t devad = MMD_CR_DEVADDR;
+ // int32_t status;
- ENETTRACE_VERBOSE("PHY %u: write %u val 0x%04x\n", hPhy->addr, reg, val);
+ // ENETTRACE_VERBOSE("PHY %u: write %u val 0x%04x\n", hPhy->addr, reg, val);
- status = EnetPhy_writeReg(hPhy, PHY_MMD_CR, devad | MMD_CR_ADDR);
- if (status == ENETPHY_SOK)
- {
- EnetPhy_writeReg(hPhy, PHY_MMD_DR, reg);
- }
+ // status = EnetPhy_writeReg(hPhy, PHY_MMD_CR, devad | MMD_CR_ADDR);
+ // if (status == ENETPHY_SOK)
+ // {
+ // EnetPhy_writeReg(hPhy, PHY_MMD_DR, reg);
+ // }
- if (status == ENETPHY_SOK)
- {
- EnetPhy_writeReg(hPhy, PHY_MMD_CR, devad | MMD_CR_DATA_NOPOSTINC);
- }
+ // if (status == ENETPHY_SOK)
+ // {
+ // EnetPhy_writeReg(hPhy, PHY_MMD_CR, devad | MMD_CR_DATA_NOPOSTINC);
+ // }
- if (status == ENETPHY_SOK)
- {
- EnetPhy_writeReg(hPhy, PHY_MMD_DR, val);
- }
+ // if (status == ENETPHY_SOK)
+ // {
+ // EnetPhy_writeReg(hPhy, PHY_MMD_DR, val);
+ // }
- ENETTRACE_ERR_IF(status != ENETPHY_SOK,
- "PHY %u: failed to write reg %u val 0x%04x\n", hPhy->addr, reg, val);
+ // ENETTRACE_ERR_IF(status != ENETPHY_SOK,
+ // "PHY %u: failed to write reg %u val 0x%04x\n", hPhy->addr, reg, val);
- return status;
+ // return status;
+ return ENETPHY_SOK;
}
+
+// void thoumaster(EnetPhy_Handle hPhy);
+// void thouslave(EnetPhy_Handle hPhy);
+// void hunmaster(EnetPhy_Handle hPhy);
+// void hunslave(EnetPhy_Handle hPhy);
void GenericPhy_printRegs(EnetPhy_Handle hPhy)
{
uint32_t i;
@@ -207,3 +304,542 @@ void GenericPhy_printRegs(EnetPhy_Handle hPhy)
EnetUtils_printf("PHY %u: reg 0x%02x = 0x%04x\n", hPhy->addr, i, val);
}
}
+
+/* phy config */
+int g_master = 1;
+int g_speed = 100;
+int g_loopback = 0;
+/* end of phy config */
+
+int g_DEVAD = 1;
+// static void Bcm89881_config(EnetPhy_Handle hPhy)
+// {
+// EnetUtils_printf("Bcm89881_config start, master:%d, speed:%d, loopback:%d\n",
+// g_master, g_speed, g_loopback);
+
+// /* master mode */
+// if (g_master) {
+// if (g_speed == 1000)
+// thoumaster(hPhy);
+// else if (g_speed == 100)
+// hunmaster(hPhy);
+// return;
+// }
+
+// /* slave mode */
+// if (g_speed == 1000)
+// thouslave(hPhy);
+// else if (g_speed == 100)
+// hunslave(hPhy);
+// }
+
+static void thouslave(EnetPhy_Handle hPhy)
+{
+ g_DEVAD = 0x01;
+
+ EnetPhy_writeReg(hPhy, 0x0000, 0x8040); // 'reset
+
+ uint16_t TC10_ctrl, SuperIsolate;
+ uint16_t TC10_disable;
+ uint16_t val;
+ uint16_t Speed = 1000;
+
+ g_DEVAD = 0x1E;
+ EnetPhy_readReg(hPhy, 0x00F0, &TC10_ctrl);
+ g_DEVAD = 0x01;
+ TC10_disable = TC10_ctrl & 0x8000; // 'RXDV/PAR_EN strapped low
+ EnetPhy_readReg(hPhy, 0x932A, &val);
+ SuperIsolate = val & 0x0020;
+
+ if (TC10_disable == 0x0000 ) { // Then ' TC10 is enabled
+ EnetPhy_writeReg(hPhy, 0x8F02, 0x0001);
+ if (Speed == 1000) { //Then 'TC10 enabled
+ g_DEVAD = 0x1E;
+ EnetPhy_writeReg(hPhy, 0x00F0, TC10_ctrl | 0x800); // 'if 1G and TC10 is enabled, through register disable TC10
+ EnetPhy_writeReg(hPhy, 0x00F0, TC10_ctrl);
+ g_DEVAD = 0x01;
+ }
+ } else if (SuperIsolate == 0x0) { //'Super Isolate is OFF
+ EnetPhy_writeReg(hPhy, 0x8F02, 0x0001);
+ }
+ EnetPhy_writeReg(hPhy, 0x900B, 0x0000);
+ EnetPhy_writeReg(hPhy, 0x0834, 0x8001); //'1G Slave-0x8001
+ EnetPhy_writeReg(hPhy, 0xa010, 0x0101);//RXC,TXC delay
+ Board_delay(200); // added by xjb
+
+ if (g_loopback == 1) {
+ g_DEVAD = 0x03;
+ EnetPhy_readReg(hPhy, 0x0000, &val);
+ val |= 0x4000;
+ EnetPhy_writeReg(hPhy, 0x0000, val);
+ g_DEVAD = 0x01;
+ }
+
+ g_DEVAD = 0x07;
+ EnetPhy_writeReg(hPhy, 0x0200, 0x0200);
+ g_DEVAD = 0x01;
+
+ if (TC10_disable == 0x0000 || SuperIsolate == 0x0) // Then ' TC10 is enabled, superisolate is OFF
+ EnetPhy_writeReg(hPhy, 0x8F02, 0x0000); // 'To enable port
+ else
+ EnetPhy_writeReg(hPhy, 0x932A, 0x0002); // ' To disable superisolate
+
+ EnetPhy_writeReg(hPhy, 0x931D, 0x3410); // 'CORE_MISC_SHD1C_0D
+ EnetPhy_writeReg(hPhy, 0x931E, 0x3863); // 'CORE_MISC_SHD1C_0E
+ EnetPhy_writeReg(hPhy, 0xA027, 0x0317); // 'TOP_MISC_LED_INTR_CTL
+ EnetPhy_writeReg(hPhy, 0x9319, 0x2508); // 'CORE_MISC_SHD1C_09
+}
+static void thoumaster(EnetPhy_Handle hPhy)
+{
+ g_DEVAD = 0x01;
+
+ EnetPhy_writeReg(hPhy, 0x0000, 0x8040); // 'reset
+
+ uint16_t TC10_ctrl, SuperIsolate;
+ uint16_t TC10_disable;
+ uint16_t val;
+ uint16_t Speed = 1000;
+
+ g_DEVAD = 0x1E;
+ EnetPhy_readReg(hPhy, 0x00F0, &TC10_ctrl);
+ g_DEVAD = 0x01;
+ TC10_disable = TC10_ctrl & 0x8000; // 'RXDV/PAR_EN strapped low
+ EnetPhy_readReg(hPhy, 0x932A, &val);
+ SuperIsolate = val & 0x0020;
+
+ if (TC10_disable == 0x0000 ) { // Then ' TC10 is enabled
+ EnetPhy_writeReg(hPhy, 0x8F02, 0x0001);
+ if (Speed == 1000) { //Then 'TC10 enabled
+ g_DEVAD = 0x1E; //内部寄存器
+ EnetPhy_writeReg(hPhy, 0x00F0, TC10_ctrl | 0x800); // 'if 1G and TC10 is enabled, through register disable TC10
+ EnetPhy_writeReg(hPhy, 0x00F0, TC10_ctrl);
+ g_DEVAD = 0x01;
+ }
+ } else if (SuperIsolate == 0x0) { //'Super Isolate is OFF
+ EnetPhy_writeReg(hPhy, 0x8F02, 0x0001);
+ }
+
+ EnetPhy_writeReg(hPhy, 0x900B, 0x0000);
+ EnetPhy_writeReg(hPhy, 0x0834, 0xC001); // '1G master
+ EnetPhy_writeReg(hPhy, 0xa010, 0x0101);//RXC,TXC delay
+ Board_delay(200); // added by xjb
+
+ if (g_loopback == 1) {
+ g_DEVAD = 0x03;
+ EnetPhy_readReg(hPhy, 0x0000, &val);
+ val |= 0x4000;
+ EnetPhy_writeReg(hPhy, 0x0000, val);
+ g_DEVAD = 0x01;
+ }
+
+ g_DEVAD = 0x07;
+ EnetPhy_writeReg(hPhy, 0x0200, 0x0200);
+ g_DEVAD = 0x01;
+
+ if (TC10_disable == 0x0000 || SuperIsolate == 0x0) // Then ' TC10 is enabled, superisolate is OFF
+ EnetPhy_writeReg(hPhy, 0x8F02, 0x0000); // 'To enable port
+ else
+ EnetPhy_writeReg(hPhy, 0x932A, 0x0002); // ' To disable superisolate
+
+ EnetPhy_writeReg(hPhy, 0x931D, 0x3410); // 'CORE_MISC_SHD1C_0D
+ EnetPhy_writeReg(hPhy, 0x931E, 0x3863); // 'CORE_MISC_SHD1C_0E
+ EnetPhy_writeReg(hPhy, 0xA027, 0x0317); // 'TOP_MISC_LED_INTR_CTL
+ EnetPhy_writeReg(hPhy, 0x9319, 0x2508); // 'CORE_MISC_SHD1C_09
+}
+
+static void hunslave(EnetPhy_Handle hPhy)
+{
+ g_DEVAD = 0x01;
+
+ EnetPhy_writeReg(hPhy,0x8130,0x798d);
+ EnetPhy_writeReg(hPhy,0x8131,0x0688);
+ EnetPhy_writeReg(hPhy,0x8132,0xa405);
+ EnetPhy_writeReg(hPhy,0x8133,0x2110);
+ EnetPhy_writeReg(hPhy,0x8134,0xbf04);
+ EnetPhy_writeReg(hPhy,0x8135,0x1818);
+ EnetPhy_writeReg(hPhy,0x8136,0x2181);
+ EnetPhy_writeReg(hPhy,0x8140,0x94a9);
+ EnetPhy_writeReg(hPhy,0x8141,0x0688);
+ EnetPhy_writeReg(hPhy,0x8142,0xa405);
+ EnetPhy_writeReg(hPhy,0x8143,0x2110);
+ EnetPhy_writeReg(hPhy,0x8144,0xbf84);
+ EnetPhy_writeReg(hPhy,0x8145,0x1818);
+ EnetPhy_writeReg(hPhy,0x8146,0x0209);
+
+ EnetPhy_writeReg(hPhy,0x81d0,0x009d);
+ EnetPhy_writeReg(hPhy,0x81d1,0x8000);
+ EnetPhy_writeReg(hPhy,0x81d2,0x0000);
+ EnetPhy_writeReg(hPhy,0x81d3,0x0104);
+ EnetPhy_writeReg(hPhy,0x81d4,0x7f04);
+ EnetPhy_writeReg(hPhy,0x81d5,0x1a18);
+ EnetPhy_writeReg(hPhy,0x81d6,0x002d);
+ EnetPhy_writeReg(hPhy,0x81e0,0x7eef);
+ EnetPhy_writeReg(hPhy,0x81e1,0x800a);
+ EnetPhy_writeReg(hPhy,0x81e2,0x0007);
+ EnetPhy_writeReg(hPhy,0x81e3,0x0014);
+ EnetPhy_writeReg(hPhy,0x81e4,0x0300);
+ EnetPhy_writeReg(hPhy,0x81e5,0x893e);
+ EnetPhy_writeReg(hPhy,0x81e6,0x25bf);
+ EnetPhy_writeReg(hPhy,0x81f0,0x007e);
+ EnetPhy_writeReg(hPhy,0x81f1,0x6f95);
+ EnetPhy_writeReg(hPhy,0x81f2,0x0000);
+ EnetPhy_writeReg(hPhy,0x81f3,0x0014);
+ EnetPhy_writeReg(hPhy,0x81f4,0x0300);
+ EnetPhy_writeReg(hPhy,0x81f5,0x893e);
+ EnetPhy_writeReg(hPhy,0x81f6,0x25bf);
+
+ EnetPhy_writeReg(hPhy,0x8030,0xe005);
+ EnetPhy_writeReg(hPhy,0x8031,0xe294);
+ EnetPhy_writeReg(hPhy,0x8033,0xed9c);
+ EnetPhy_writeReg(hPhy,0x8032,0xe4a8);
+
+ EnetPhy_writeReg(hPhy,0x0834,0x8000); //100M Slave
+
+ EnetPhy_writeReg(hPhy,0xa010,0x0101);//RXC,TXC delay
+
+ Board_delay(100);
+
+ if (g_loopback == 1) {
+ uint16_t val = 0;
+ g_DEVAD = 0x03;
+ EnetPhy_readReg(hPhy, 0x0000, &val);
+ val |= 0x4000;
+ EnetPhy_writeReg(hPhy, 0x0000, val);
+ g_DEVAD = 0x01;
+ }
+
+ g_DEVAD = 0x07;
+ EnetPhy_writeReg(hPhy, 0x0200, 0x0200); //Restart link
+ g_DEVAD = 0x01;
+
+ EnetPhy_writeReg(hPhy,0x931D,0x3410);
+ EnetPhy_writeReg(hPhy,0x931E,0x3863);
+ EnetPhy_writeReg(hPhy,0xA027,0x0317);
+ EnetPhy_writeReg(hPhy,0x9319,0x2508);
+}
+
+static void hunmaster(EnetPhy_Handle hPhy)
+{
+ g_DEVAD = 0x01;
+
+ EnetPhy_writeReg(hPhy, 0x8130, 0x798d);
+ EnetPhy_writeReg(hPhy, 0x8131, 0x0688);
+ EnetPhy_writeReg(hPhy, 0x8132, 0xa405);
+ EnetPhy_writeReg(hPhy, 0x8133, 0x2110);
+ EnetPhy_writeReg(hPhy, 0x8134, 0xbf04);
+ EnetPhy_writeReg(hPhy, 0x8135, 0x1818);
+ EnetPhy_writeReg(hPhy, 0x8136, 0x2181);
+ EnetPhy_writeReg(hPhy, 0x8140, 0x94a9);
+ EnetPhy_writeReg(hPhy, 0x8141, 0x0688);
+ EnetPhy_writeReg(hPhy, 0x8142, 0xa405);
+ EnetPhy_writeReg(hPhy, 0x8143, 0x2110);
+ EnetPhy_writeReg(hPhy, 0x8144, 0xbf84);
+ EnetPhy_writeReg(hPhy, 0x8145, 0x1818);
+ EnetPhy_writeReg(hPhy, 0x8146, 0x0209);
+
+ EnetPhy_writeReg(hPhy, 0x81d0, 0x009d);
+ EnetPhy_writeReg(hPhy, 0x81d1, 0x8000);
+ EnetPhy_writeReg(hPhy, 0x81d2, 0x0000);
+ EnetPhy_writeReg(hPhy, 0x81d3, 0x0104);
+ EnetPhy_writeReg(hPhy, 0x81d4, 0x7f04);
+ EnetPhy_writeReg(hPhy, 0x81d5, 0x1a18);
+ EnetPhy_writeReg(hPhy, 0x81d6, 0x002d);
+ EnetPhy_writeReg(hPhy, 0x81e0, 0x7eef);
+ EnetPhy_writeReg(hPhy, 0x81e1, 0x800a);
+ EnetPhy_writeReg(hPhy, 0x81e2, 0x0007);
+ EnetPhy_writeReg(hPhy, 0x81e3, 0x0014);
+ EnetPhy_writeReg(hPhy, 0x81e4, 0x0300);
+ EnetPhy_writeReg(hPhy, 0x81e5, 0x893e);
+ EnetPhy_writeReg(hPhy, 0x81e6, 0x25bf);
+ EnetPhy_writeReg(hPhy, 0x81f0, 0x007e);
+ EnetPhy_writeReg(hPhy, 0x81f1, 0x6f95);
+ EnetPhy_writeReg(hPhy, 0x81f2, 0x0000);
+ EnetPhy_writeReg(hPhy, 0x81f3, 0x0014);
+ EnetPhy_writeReg(hPhy, 0x81f4, 0x0300);
+ EnetPhy_writeReg(hPhy, 0x81f5, 0x893e);
+ EnetPhy_writeReg(hPhy, 0x81f6, 0x25bf);
+
+ EnetPhy_writeReg(hPhy, 0x8030, 0xe005);
+ EnetPhy_writeReg(hPhy, 0x8031, 0xe179);
+ EnetPhy_writeReg(hPhy, 0x8033, 0xee7d);
+ EnetPhy_writeReg(hPhy, 0x8032, 0xe38c);
+
+ EnetPhy_writeReg(hPhy, 0x0834, 0xC000); //100M Master
+
+ EnetPhy_writeReg(hPhy, 0xa010, 0x0101); //RXC,TXC delay
+
+ printf("[LXC]: hunmaster1111 finished. hPhy->addr = %d\n", hPhy->addr);
+
+ if (g_loopback == 1) {
+ uint16_t val = 0;
+ g_DEVAD = 0x03;
+ EnetPhy_readReg(hPhy, 0x0000, &val);
+ val |= 0x4000;
+ EnetPhy_writeReg(hPhy, 0x0000, val);
+ g_DEVAD = 0x01;
+ }
+
+ printf("[LXC]: hunmaster2222 finished. hPhy->addr = %d\n", hPhy->addr);
+
+ Board_delay(100);
+
+ g_DEVAD = 0x07;
+ EnetPhy_writeReg(hPhy, 0x0200, 0x0200); //Restart link
+ g_DEVAD = 0x01;
+
+ EnetPhy_writeReg(hPhy, 0x931D, 0x3410);
+ EnetPhy_writeReg(hPhy, 0x931E, 0x3863);
+ EnetPhy_writeReg(hPhy, 0xA027, 0x0317);
+ EnetPhy_writeReg(hPhy, 0x9319, 0x2508);
+}
+
+// void GenericPhy_printRegs(EnetPhy_Handle hPhy)
+static void Bcm89881_config(EnetPhy_Handle hPhy)
+{
+ EnetUtils_printf("Bcm89881_config start, master:%d, speed:%d, loopback:%d\n",
+ g_master, g_speed, g_loopback);
+
+ printf("[LXC]: Bcm89881_config hPhy->addr = %d\n", hPhy->addr);
+
+ /* master mode */
+ if (g_master) {
+ if (g_speed == 1000)
+ thoumaster(hPhy);
+ else if (g_speed == 100)
+ hunmaster(hPhy);
+ return;
+ }
+
+ printf("[LXC]: Bcm89881_config g_speed = %d\n", g_speed);
+
+ /* slave mode */
+ if (g_speed == 1000)
+ thouslave(hPhy);
+ else if (g_speed == 100)
+ hunslave(hPhy);
+}
+
+static void ACD_init(EnetPhy_Handle hPhy)
+{
+ // All-PHY Select
+ int LP = 0; // 1 for LP = Polar 0 for LP = others
+ int Leoni_cable_type_647 = 1; // 1 for 647 0 for 545
+ uint16_t ACD_mode_reg_value;
+
+ g_DEVAD = 0x01;
+
+ EnetPhy_readReg(hPhy, 0xA000, &ACD_mode_reg_value);
+ EnetPhy_writeReg(hPhy, 0xA000, 0x4 | ACD_mode_reg_value);
+ EnetPhy_writeReg(hPhy, 0xA2A7, 0x0202);
+ EnetPhy_writeReg(hPhy, 0xA2A8, 0x7f50);
+
+ if (LP == 1)
+ EnetPhy_writeReg(hPhy, 0xA2A9, 0xaC22);
+ else
+ EnetPhy_writeReg(hPhy, 0xA2A9, 0x2C22);
+
+ if (Leoni_cable_type_647 == 1)
+ EnetPhy_writeReg(hPhy, 0xA2AA, 0x5252);
+ else
+ EnetPhy_writeReg(hPhy, 0xA2AA, 0xD252);
+
+ EnetPhy_writeReg(hPhy, 0xA2Ab, 0x0);
+ EnetPhy_writeReg(hPhy, 0xA2Ac, 0x0094);
+ EnetPhy_writeReg(hPhy, 0xA2Ae, 0x1CA3);
+ EnetPhy_writeReg(hPhy, 0xA2Af, 0x0206);
+
+ // ---------------------------------------------------------------------------------
+ // ------- page // 01//
+ // ---------------------------------------------------------------------------------
+ EnetPhy_writeReg(hPhy, 0xA2b0, 0x0010);
+ EnetPhy_writeReg(hPhy, 0xA2b1, 0xD0D);
+ EnetPhy_writeReg(hPhy, 0xA2b2, 0x0000);
+ EnetPhy_writeReg(hPhy, 0xA2b3, 0x7700);
+ EnetPhy_writeReg(hPhy, 0xA2b4, 0x0000);
+ EnetPhy_writeReg(hPhy, 0xA2b7, 0x0);
+
+ // ---------------------------------------------------------------------------------
+ // --- Now load values
+ EnetPhy_writeReg(hPhy, 0xA2bf, 0x409F);
+ EnetPhy_writeReg(hPhy, 0xA2ad, 0x1129);
+ EnetPhy_writeReg(hPhy, 0xA2ad, 0x0129);
+ EnetPhy_writeReg(hPhy, 0xA2b0, 0x0);
+ EnetPhy_writeReg(hPhy, 0xA2b1, 0x0);
+ EnetPhy_writeReg(hPhy, 0xA2b2, 0x0);
+ EnetPhy_writeReg(hPhy, 0xA2b3, 0x0);
+ EnetPhy_writeReg(hPhy, 0xA2b4, 0x0);
+ EnetPhy_writeReg(hPhy, 0xA2b7, 0x0);
+ EnetPhy_writeReg(hPhy, 0xA2bf, 0x0);
+
+ // ---------------------------------------------------------------------------------
+ // ------- page // 10//
+ // ---------------------------------------------------------------------------------
+ EnetPhy_writeReg(hPhy, 0xA2b0, 0x3619);
+ EnetPhy_writeReg(hPhy, 0xA2b1, 0x343A);
+ EnetPhy_writeReg(hPhy, 0xA2b2, 0x0);
+ EnetPhy_writeReg(hPhy, 0xA2b3, 0x0);
+ EnetPhy_writeReg(hPhy, 0xA2b4, 0x8000);
+ EnetPhy_writeReg(hPhy, 0xA2b5, 0x000E);
+ EnetPhy_writeReg(hPhy, 0xA2b7, 0x0);
+ EnetPhy_writeReg(hPhy, 0xA2b9, 0x0400);
+ EnetPhy_writeReg(hPhy, 0xA2bd, 0x0);
+
+ // ---------------------------------------------------------------------------------
+ // --- Now load values
+ EnetPhy_writeReg(hPhy, 0xA2bf, 0xA2BF);
+ EnetPhy_writeReg(hPhy, 0xA2ad, 0x1129);
+ EnetPhy_writeReg(hPhy, 0xA2ad, 0x0129);
+ EnetPhy_writeReg(hPhy, 0xA2b0, 0x0);
+ EnetPhy_writeReg(hPhy, 0xA2b1, 0x0);
+ EnetPhy_writeReg(hPhy, 0xA2b2, 0x0);
+ EnetPhy_writeReg(hPhy, 0xA2b3, 0x0);
+ EnetPhy_writeReg(hPhy, 0xA2b4, 0x0);
+ EnetPhy_writeReg(hPhy, 0xA2b5, 0x0);
+ EnetPhy_writeReg(hPhy, 0xA2b7, 0x0);
+ EnetPhy_writeReg(hPhy, 0xA2b9, 0x0);
+ EnetPhy_writeReg(hPhy, 0xA2bd, 0x0);
+ EnetPhy_writeReg(hPhy, 0xA2bf, 0x0);
+}
+
+#define ECD_INVALID 0
+#define ECD_NO_FAULT 1
+#define ECD_OPEN 2
+#define ECD_SHORT 3
+#define ECD_PIN_SHORT_OR_XT 4
+#define ECD_FORCED 5
+static void ACD_run(EnetPhy_Handle hPhy)
+{
+ const int N_BUSY_CYCLE_WAIT = 300;
+ const uint16_t ERROR_ECD_BUSY_ON_DEMAND = 0x1;
+ // const uint16_t ERROR_ECD_BUSY_DURING_FLUSH = 0x2;
+ // const uint16_t ERROR_ECD_INVALID = 0x4;
+ const uint16_t ERROR_ECD_NO_NEW_RESULT = 0x8;
+
+ int k, open_threshold, fault;
+ uint16_t temp_A;
+ uint16_t EXP_C[11], faultType[3], error_flag;
+ float distanceCm[3];
+ float length_factor, peak_amplitude;
+ int new_result;
+ int LP, m, cable_type;
+ char* lkup[6];
+
+ lkup[0] = "INVALID";
+ lkup[1] = "NO_FAULT";
+ lkup[2] = "OPEN";
+ lkup[3] = "SHORT";
+ lkup[4] = "PIN SHORT or CrossTalk";
+ lkup[5] = "FORCED";
+ error_flag = 0;
+ g_DEVAD = 0x01;
+
+ EnetPhy_writeReg(hPhy, 0xA2A0, 0x400);
+ EnetPhy_writeReg(hPhy, 0xA2A0, 0x8400);
+
+ // ----- Looping For ECD done ---------------------
+ new_result = 0;
+
+ for(k = 1; k <= N_BUSY_CYCLE_WAIT; k++) {
+ for(m = 0; m <= 10; m++) {
+ EnetPhy_readReg(hPhy, 0xA2A0 + m, EXP_C + m);
+ }
+ if ((EXP_C[0] & 0x4) != 0) // There is new ECD result
+ new_result = 1;
+ if ((EXP_C[0] & 0x800) == 0)
+ break;
+ }
+
+ if (k >= N_BUSY_CYCLE_WAIT)
+ error_flag = error_flag | ERROR_ECD_BUSY_ON_DEMAND;
+ if (new_result == 0)
+ error_flag = error_flag | ERROR_ECD_NO_NEW_RESULT;
+
+ if ((EXP_C[9] & 0x8000) != 0)
+ LP = 1;
+ else
+ LP = 0;
+
+ if ((EXP_C[10] & 0x8000) != 0)
+ cable_type = 1;
+ else
+ cable_type = 0;
+
+ if ((EXP_C[0] & 0x400) == 0)
+ length_factor = 100;
+ else
+ length_factor = 1;
+
+ // ----- Convert fault types and cable length to BRCM DVT standard format -----
+ for(k = 0; k <= 0; k++) { // loop through each pair
+ faultType[k] = ECD_OPEN;
+ distanceCm[k] = 0;
+ }
+ temp_A = EXP_C[1] / 4096;
+ faultType[0] = EXP_C[1];
+
+ if (cable_type == 0)
+ distanceCm[0] = 0.8096 * ((float)(EXP_C[6] + EXP_C[4]) / 2) * length_factor - 1.6009;
+ else
+ distanceCm[0] = 0.807 * ((float)(EXP_C[6] + EXP_C[4]) / 2) * length_factor - 2.4191;
+
+ peak_amplitude = (EXP_C[5] + EXP_C[3]) / 2;
+ open_threshold = 104;
+
+ fault = temp_A & 0xF;
+ switch(fault) {
+ case ECD_INVALID:
+ faultType[0] = ECD_INVALID;
+ break;
+ case ECD_NO_FAULT: // fault = 1
+ faultType[0] = ECD_NO_FAULT;
+ break;
+ case ECD_OPEN: // fault = 2
+ faultType[0] = ECD_OPEN;
+ if (LP == 0) {
+ if (peak_amplitude < open_threshold) {
+ faultType[0] = ECD_NO_FAULT;
+ if (cable_type == 0)
+ distanceCm[0] = 0.807 * ((float)(EXP_C[6] + EXP_C[4]) / 2) * length_factor - 2.4191;
+ else
+ distanceCm[0] = 1.1987 * ((float)((EXP_C[6] + EXP_C[4]) / 2 - 2.073) * 0.6558 * length_factor - 0.2246) - 0.3482;
+ }
+ } else { // This is for Polar
+ if (peak_amplitude < 100) {
+ faultType[0] = ECD_NO_FAULT;
+ if (cable_type == 0)
+ distanceCm[0] = 0.818 * ((float)(EXP_C[6] + EXP_C[4]) / 2) * length_factor - 4.9381;
+ else
+ distanceCm[0] = 1.2043 * ((float)((EXP_C[6] + EXP_C[4]) / 2 - 5.0266) * 0.6626 * length_factor - 0.2246) - 0.3747;
+ }
+ }
+ break;
+ case ECD_SHORT:
+ faultType[0] = ECD_SHORT;
+ if (cable_type == 0)
+ distanceCm[0] = 0.7949 * ((float)(EXP_C[6] + EXP_C[4]) / 2) * length_factor - 1.6385;
+ else
+ distanceCm[0] = 1.2389 * (((float)(EXP_C[6] + EXP_C[4]) / 2 - 1.7506) * 0.6615 * length_factor - 0.2246) - 0.3344;
+ break;
+ case ECD_PIN_SHORT_OR_XT:
+ faultType[0] = ECD_PIN_SHORT_OR_XT;
+ break;
+ case ECD_FORCED:
+ faultType[0] = ECD_FORCED;
+ break;
+ default:
+ faultType[0] = ECD_INVALID;
+ }
+
+ if (distanceCm[0] < 0)
+ distanceCm[0] = 0;
+
+ EnetUtils_printf("Cable Diag Result: FaultType = %u(%s), Distance(cm) = %f\n",
+ faultType[0], lkup[faultType[0]], distanceCm[0]);
+}
+
+void ACD_test(EnetPhy_Handle hPhy)
+{
+ ACD_init(hPhy);
+ Board_delay(100);
+ ACD_run(hPhy);
+}
The pdk_patch 2:
diff --git a/packages/ti/board/src/j721e_evm/J721E_pinmux_data_gesi_cpsw9g.c b/packages/ti/board/src/j721e_evm/J721E_pinmux_data_gesi_cpsw9g.c
index 64c6b82..48bcb9c 100755
--- a/packages/ti/board/src/j721e_evm/J721E_pinmux_data_gesi_cpsw9g.c
+++ b/packages/ti/board/src/j721e_evm/J721E_pinmux_data_gesi_cpsw9g.c
@@ -47,10 +47,10 @@ static pinmuxPerCfg_t gGpio0PinCfg[] =
// ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
// },
/* MyGPIO0 -> GPIO0_104 -> W26 */
- {
- PIN_RGMII6_RXC, PIN_MODE(7) | \
- ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
- },
+ // {
+ // PIN_RGMII6_RXC, PIN_MODE(7) | \
+ // ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
+ // },
{PINMUX_END}
};
@@ -63,12 +63,12 @@ static pinmuxModuleCfg_t gGpioPinCfg[] =
static pinmuxPerCfg_t gMdio0PinCfg[] =
{
- /* MyMDIO1 -> MDIO0_MDC -> V24 */
+ /* Port56_MDC -> MDIO0_MDC -> V24 */
{
PIN_MDIO0_MDC, PIN_MODE(0) | \
((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))
},
- /* MyMDIO1 -> MDIO0_MDIO -> V26 */
+ /* Port56_MDIO -> MDIO0_MDIO -> V26 */
{
PIN_MDIO0_MDIO, PIN_MODE(0) | \
((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
@@ -76,6 +76,36 @@ static pinmuxPerCfg_t gMdio0PinCfg[] =
{PINMUX_END}
};
+// static pinmuxPerCfg_t gMdio1PinCfg[] =
+// {
+// /* Port1_MDC -> PIN_PRG1_MDIO0_MDC -> AD18 */
+// {
+// PIN_PRG1_MDIO0_MDC, PIN_MODE(0) | \
+// ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))
+// },
+// /* Port1_MDC -> PIN_PRG1_MDIO0_MDIO -> AD19 */
+// {
+// PIN_PRG1_MDIO0_MDIO, PIN_MODE(0) | \
+// ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
+// },
+// {PINMUX_END}
+// };
+
+// static pinmuxPerCfg_t gMdio2PinCfg[] =
+// {
+// /* Port3_MDC -> PIN_PRG0_MDIO0_MDC -> AA27 */
+// {
+// PIN_PRG0_MDIO0_MDC, PIN_MODE(0) | \
+// ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))
+// },
+// /* Port3_MDC -> PIN_PRG0_MDIO0_MDIO -> Y26 */
+// {
+// PIN_PRG0_MDIO0_MDIO, PIN_MODE(0) | \
+// ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
+// },
+// {PINMUX_END}
+// };
+
// static pinmuxPerCfg_t gMdio0PinCfg[] =
// {
// /* MyMDIO1 -> PIN_PRG1_MDIO0_MDC -> AD18 */
@@ -94,6 +124,8 @@ static pinmuxPerCfg_t gMdio0PinCfg[] =
static pinmuxModuleCfg_t gMdioPinCfg[] =
{
{0, TRUE, gMdio0PinCfg},
+ // {1, TRUE, gMdio1PinCfg},
+ // {2, TRUE, gMdio2PinCfg},
{PINMUX_END}
};
@@ -423,71 +455,136 @@ static pinmuxPerCfg_t gRgmii5PinCfg[] =
{PINMUX_END}
};
-static pinmuxPerCfg_t gRgmii7PinCfg[] =
+static pinmuxPerCfg_t gRgmii6PinCfg[] =
{
- /* MyRGMII7 -> RGMII7_RD0 -> AC23 */
+ /* MyRGMII6 -> RGMII6_RD0 */
{
- PIN_PRG1_PRU0_GPO0, PIN_MODE(9) | \
+ PIN_RGMII6_RD0, PIN_MODE(0) | \
((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
},
- /* MyRGMII7 -> RGMII7_RD1 -> AG22 */
+ /* MyRGMII6 -> RGMII6_RD1 */
{
- PIN_PRG1_PRU0_GPO1, PIN_MODE(9) | \
+ PIN_RGMII6_RD1, PIN_MODE(0) | \
((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
},
- /* MyRGMII7 -> RGMII7_RD2 -> AF22 */
+ /* MyRGMII6 -> RGMII6_RD2 */
{
- PIN_PRG1_PRU0_GPO2, PIN_MODE(9) | \
+ PIN_RGMII6_RD2, PIN_MODE(0) | \
((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
},
- /* MyRGMII7 -> RGMII7_RD3 -> AJ23 */
+ /* MyRGMII6 -> RGMII6_RD3 */
{
- PIN_PRG1_PRU0_GPO3, PIN_MODE(9) | \
+ PIN_RGMII6_RD3, PIN_MODE(0) | \
((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
},
- /* MyRGMII7 -> RGMII7_RXC -> AD22 */
+ /* MyRGMII6 -> RGMII6_RXC */
{
- PIN_PRG1_PRU0_GPO6, PIN_MODE(9) | \
+ PIN_RGMII6_RXC, PIN_MODE(0) | \
((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
},
- /* MyRGMII7 -> RGMII7_RX_CTL -> AH23 */
+ /* MyRGMII6 -> RGMII6_RX_CTL */
{
- PIN_PRG1_PRU0_GPO4, PIN_MODE(9) | \
+ PIN_RGMII6_RX_CTL, PIN_MODE(0) | \
((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
},
- /* MyRGMII7 -> RGMII7_TD0 -> AF24 */
+ /* MyRGMII6 -> RGMII6_TD0 */
{
- PIN_PRG1_PRU0_GPO11, PIN_MODE(9) | \
+ PIN_RGMII6_TD0, PIN_MODE(0) | \
((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))
},
- /* MyRGMII7 -> RGMII7_TD1 -> AJ24 */
+ /* MyRGMII6 -> RGMII6_TD1 */
{
- PIN_PRG1_PRU0_GPO12, PIN_MODE(9) | \
+ PIN_RGMII6_TD1, PIN_MODE(0) | \
((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))
},
- /* MyRGMII7 -> RGMII7_TD2 -> AG24 */
+ /* MyRGMII6 -> RGMII6_TD2 */
{
- PIN_PRG1_PRU0_GPO13, PIN_MODE(9) | \
+ PIN_RGMII6_TD2, PIN_MODE(0) | \
((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))
},
- /* MyRGMII7 -> RGMII7_TD3 -> AD24 */
+ /* MyRGMII6 -> RGMII6_TD3 */
{
- PIN_PRG1_PRU0_GPO14, PIN_MODE(9) | \
+ PIN_RGMII6_TD3, PIN_MODE(0) | \
((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))
},
- /* MyRGMII7 -> RGMII7_TXC -> AE24 */
+ /* MyRGMII6 -> RGMII6_TXC */
{
- PIN_PRG1_PRU0_GPO16, PIN_MODE(9) | \
+ PIN_RGMII6_TXC, PIN_MODE(0) | \
((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))
},
- /* MyRGMII7 -> RGMII7_TX_CTL -> AC24 */
+ /* MyRGMII6 -> RGMII6_TX_CTL */
{
- PIN_PRG1_PRU0_GPO15, PIN_MODE(9) | \
+ PIN_RGMII6_TX_CTL, PIN_MODE(0) | \
((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))
},
{PINMUX_END}
};
+static pinmuxPerCfg_t gRgmii7PinCfg[] =
+{
+ // /* MyRGMII7 -> RGMII7_RD0 -> AC23 */
+ // {
+ // PIN_PRG1_PRU0_GPO0, PIN_MODE(9) | \
+ // ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
+ // },
+ // /* MyRGMII7 -> RGMII7_RD1 -> AG22 */
+ // {
+ // PIN_PRG1_PRU0_GPO1, PIN_MODE(9) | \
+ // ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
+ // },
+ // /* MyRGMII7 -> RGMII7_RD2 -> AF22 */
+ // {
+ // PIN_PRG1_PRU0_GPO2, PIN_MODE(9) | \
+ // ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
+ // },
+ // /* MyRGMII7 -> RGMII7_RD3 -> AJ23 */
+ // {
+ // PIN_PRG1_PRU0_GPO3, PIN_MODE(9) | \
+ // ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
+ // },
+ // /* MyRGMII7 -> RGMII7_RXC -> AD22 */
+ // {
+ // PIN_PRG1_PRU0_GPO6, PIN_MODE(9) | \
+ // ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
+ // },
+ // /* MyRGMII7 -> RGMII7_RX_CTL -> AH23 */
+ // {
+ // PIN_PRG1_PRU0_GPO4, PIN_MODE(9) | \
+ // ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
+ // },
+ // /* MyRGMII7 -> RGMII7_TD0 -> AF24 */
+ // {
+ // PIN_PRG1_PRU0_GPO11, PIN_MODE(9) | \
+ // ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))
+ // },
+ // /* MyRGMII7 -> RGMII7_TD1 -> AJ24 */
+ // {
+ // PIN_PRG1_PRU0_GPO12, PIN_MODE(9) | \
+ // ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))
+ // },
+ // /* MyRGMII7 -> RGMII7_TD2 -> AG24 */
+ // {
+ // PIN_PRG1_PRU0_GPO13, PIN_MODE(9) | \
+ // ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))
+ // },
+ // /* MyRGMII7 -> RGMII7_TD3 -> AD24 */
+ // {
+ // PIN_PRG1_PRU0_GPO14, PIN_MODE(9) | \
+ // ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))
+ // },
+ // /* MyRGMII7 -> RGMII7_TXC -> AE24 */
+ // {
+ // PIN_PRG1_PRU0_GPO16, PIN_MODE(9) | \
+ // ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))
+ // },
+ // /* MyRGMII7 -> RGMII7_TX_CTL -> AC24 */
+ // {
+ // PIN_PRG1_PRU0_GPO15, PIN_MODE(9) | \
+ // ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))
+ // },
+ {PINMUX_END}
+};
+
static pinmuxPerCfg_t gRgmii8PinCfg[] =
{
/* MyRGMII8 -> RGMII8_RD0 -> AE22 */
@@ -556,9 +653,10 @@ static pinmuxPerCfg_t gRgmii8PinCfg[] =
static pinmuxModuleCfg_t gRgmiiPinCfg[] =
{
{3, TRUE, gRgmii3PinCfg},
- {4, TRUE, gRgmii4PinCfg},
+ // {4, TRUE, gRgmii4PinCfg},
{1, TRUE, gRgmii1PinCfg},
{5, TRUE, gRgmii5PinCfg},
+ {6, TRUE, gRgmii6PinCfg},
// {2, TRUE, gRgmii2PinCfg},
{PINMUX_END}
};
@@ -585,51 +683,51 @@ static pinmuxModuleCfg_t gQsgmiiPinCfg[] =
static pinmuxPerCfg_t gRmii8PinCfg[] =
{
- /* MyRMII8 -> RMII8_CRS_DV -> Y28 */
- {
- PIN_RGMII6_TX_CTL, PIN_MODE(1) | \
- ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
- },
- /* MyRMII8 -> RMII8_RXD0 -> W25 */
- {
- PIN_RGMII6_RD0, PIN_MODE(1) | \
- ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
- },
- /* MyRMII8 -> RMII8_RXD1 -> W24 */
- {
- PIN_RGMII6_RD1, PIN_MODE(1) | \
- ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
- },
- /* MyRMII8 -> RMII8_RX_ER -> V23 */
- {
- PIN_RGMII6_RX_CTL, PIN_MODE(1) | \
- ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
- },
- /* MyRMII8 -> RMII8_TXD0 -> W27 */
- {
- PIN_RGMII6_TD0, PIN_MODE(1) | \
- ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))
- },
- /* MyRMII8 -> RMII8_TXD1 -> V25 */
- {
- PIN_RGMII6_TD1, PIN_MODE(1) | \
- ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))
- },
- /* MyRMII8 -> RMII8_TX_EN -> W29 */
- {
- PIN_RGMII6_TXC, PIN_MODE(1) | \
- ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))
- },
+ // /* MyRMII8 -> RMII8_CRS_DV -> Y28 */
+ // {
+ // PIN_RGMII6_TX_CTL, PIN_MODE(1) | \
+ // ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
+ // },
+ // /* MyRMII8 -> RMII8_RXD0 -> W25 */
+ // {
+ // PIN_RGMII6_RD0, PIN_MODE(1) | \
+ // ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
+ // },
+ // /* MyRMII8 -> RMII8_RXD1 -> W24 */
+ // {
+ // PIN_RGMII6_RD1, PIN_MODE(1) | \
+ // ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
+ // },
+ // /* MyRMII8 -> RMII8_RX_ER -> V23 */
+ // {
+ // PIN_RGMII6_RX_CTL, PIN_MODE(1) | \
+ // ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
+ // },
+ // /* MyRMII8 -> RMII8_TXD0 -> W27 */
+ // {
+ // PIN_RGMII6_TD0, PIN_MODE(1) | \
+ // ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))
+ // },
+ // /* MyRMII8 -> RMII8_TXD1 -> V25 */
+ // {
+ // PIN_RGMII6_TD1, PIN_MODE(1) | \
+ // ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))
+ // },
+ // /* MyRMII8 -> RMII8_TX_EN -> W29 */
+ // {
+ // PIN_RGMII6_TXC, PIN_MODE(1) | \
+ // ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))
+ // },
{PINMUX_END}
};
static pinmuxPerCfg_t gRmii0PinCfg[] =
{
- /* MyRMII0 -> RMII_REF_CLK -> AD18 */
- {
- PIN_PRG1_MDIO0_MDC, PIN_MODE(5) | \
- ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
- },
+ // /* MyRMII0 -> RMII_REF_CLK -> AD18 */
+ // {
+ // PIN_PRG1_MDIO0_MDC, PIN_MODE(5) | \
+ // ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
+ // },
{PINMUX_END}
};
@@ -643,8 +741,8 @@ static pinmuxModuleCfg_t gRmiiPinCfg[] =
pinmuxBoardCfg_t gJ721E_MainPinmuxDataGesiCpsw9g[] =
{
- {0, gCpsw9gPinCfg},
- {1, gGpioPinCfg},
+ {0, gCpsw9gPinCfg}, //配置时钟引脚??????
+ {1, gGpioPinCfg}, //配置复位引脚??????
{2, gMdioPinCfg},
{3, gRgmiiPinCfg},
{4, gRmiiPinCfg},
diff --git a/packages/ti/board/src/j721e_evm/board_ethernet_config.c b/packages/ti/board/src/j721e_evm/board_ethernet_config.c
index 35584b6..21c7974 100755
--- a/packages/ti/board/src/j721e_evm/board_ethernet_config.c
+++ b/packages/ti/board/src/j721e_evm/board_ethernet_config.c
@@ -712,9 +712,10 @@ Board_STATUS Board_ethConfigCpsw9g(void)
for(portNum=0; portNum < BOARD_CPSW9G_PORT_MAX; portNum++)
{
// if ( 0U == portNum ||
- if ( 2U == portNum ||
+ if ( 1U == portNum ||
3U == portNum ||
- 4U == portNum )
+ 5U == portNum ||
+ 6U == portNum )
{
status = Board_cpsw9gEthConfig(portNum, RGMII);
// status = Board_cpsw9gEthConfig(portNum, RMII);
diff --git a/packages/ti/drv/enet/examples/enet_loopback_test/enet_loopback.c b/packages/ti/drv/enet/examples/enet_loopback_test/enet_loopback.c
index 4ba4f81..4d14472 100644
--- a/packages/ti/drv/enet/examples/enet_loopback_test/enet_loopback.c
+++ b/packages/ti/drv/enet/examples/enet_loopback_test/enet_loopback.c
@@ -516,6 +516,7 @@ static void EnetLpbk_tickTask(UArg a0,
Semaphore_pend(hSem, BIOS_WAIT_FOREVER);
/* PeriodicTick should be called from non-ISR context */
+ printf("[LXC]: EnetLpbk_tickTask enet_loopback.c \n");
Enet_periodicTick(gEnetLpbk.hEnet);
}
}
diff --git a/packages/ti/drv/enet/examples/utils/V1/enet_appboardutils_j721e_evm.c b/packages/ti/drv/enet/examples/utils/V1/enet_appboardutils_j721e_evm.c
index b461f63..4200750 100644
--- a/packages/ti/drv/enet/examples/utils/V1/enet_appboardutils_j721e_evm.c
+++ b/packages/ti/drv/enet/examples/utils/V1/enet_appboardutils_j721e_evm.c
@@ -97,6 +97,8 @@
/* Function Definitions */
/* ========================================================================== */
+#undef ENETAPPUTILS_BYPASS_QSGMII
+
#if !defined(ENETAPPUTILS_BYPASS_I2C) && defined(BUILD_MCU2_0)
static void EnetBoard_enetExpCfg(void)
{
@@ -360,8 +362,10 @@ uint32_t EnetBoard_getPhyAddr(Enet_Type enetType,
break;
case ENET_MAC_PORT_6:
- /* QSGMII port */
- phyAddr = 18U;
+ // /* QSGMII port */
+ // phyAddr = 18U;
+ /* RGMII port */
+ phyAddr = 1U;
break;
case ENET_MAC_PORT_7:
@@ -533,14 +537,16 @@ void EnetBoard_setPhyConfigRgmii(Enet_Type enetType,
* GESI board: 0, 1, 2, 3
* SGMII board: 2, 3, 6, 7
* QSGMII board: 0, 2, 3, 7
+ * untouch RGMII: 0, 2, 4, 5, port 1, 3, 5, 6
*/
EnetAppUtils_assert((portNum == ENET_MAC_PORT_1) ||
- (portNum == ENET_MAC_PORT_2) ||
+ // (portNum == ENET_MAC_PORT_2) ||
(portNum == ENET_MAC_PORT_3) ||
- (portNum == ENET_MAC_PORT_4) ||
+ // (portNum == ENET_MAC_PORT_4) ||
(portNum == ENET_MAC_PORT_5) ||
- (portNum == ENET_MAC_PORT_7) ||
- (portNum == ENET_MAC_PORT_8));
+ // (portNum == ENET_MAC_PORT_7) ||
+ (portNum == ENET_MAC_PORT_6));
+ // (portNum == ENET_MAC_PORT_8));
EnetBoard_setEnetControl(enetType, 0U/* instId */, portNum, RGMII);
#elif defined (SOC_J7200)
if (enetType == ENET_CPSW_2G)
@@ -632,9 +638,8 @@ void EnetBoard_setPhyConfig(Enet_Type enetType,
case ENET_CPSW_9G:
if ( ENET_MAC_PORT_1 == portNum ||
ENET_MAC_PORT_3 == portNum ||
- ENET_MAC_PORT_4 == portNum ||
ENET_MAC_PORT_5 == portNum ||
- ENET_MAC_PORT_8 == portNum )
+ ENET_MAC_PORT_6 == portNum )
{
EnetBoard_setPhyConfigRgmii(enetType,
portNum,
diff --git a/packages/ti/drv/enet/examples/utils/V1/enet_board_pinmux.c b/packages/ti/drv/enet/examples/utils/V1/enet_board_pinmux.c
index 726c756..f0606e4 100644
--- a/packages/ti/drv/enet/examples/utils/V1/enet_board_pinmux.c
+++ b/packages/ti/drv/enet/examples/utils/V1/enet_board_pinmux.c
@@ -85,7 +85,7 @@ int32_t EnetBoard_configEthFwPinmux (void)
BOARD_SOC_DOMAIN_MAIN);
/* Overwrite the ICSSG RGMII muc configurations with CPSW */
/* Below is CPSW9G QSGMII pinmux configuration,
- RGMII Ports - 1,3,4,8. QSGMII ports - 2,5,6,7 */
+ RGMII Ports - 1,3,5,6. QSGMII ports - 2,4,7,8 */
// Board_pinmuxUpdate(gJ721E_MainPinmuxDataGesiCpsw9gQsgmii,
Board_pinmuxUpdate(gJ721E_MainPinmuxDataGesiCpsw9g,
BOARD_SOC_DOMAIN_MAIN);
diff --git a/packages/ti/drv/enet/examples/utils/enet_mcm.c b/packages/ti/drv/enet/examples/utils/enet_mcm.c
index 1cc7911..6928921 100644
--- a/packages/ti/drv/enet/examples/utils/enet_mcm.c
+++ b/packages/ti/drv/enet/examples/utils/enet_mcm.c
@@ -41,6 +41,7 @@
/* ========================================================================== */
/* This is needed for memset/memcpy */
#include <string.h>
+#include <stdio.h>
#include <xdc/std.h>
#include <xdc/runtime/Error.h>
@@ -863,6 +864,7 @@ static void EnetMcm_periodicTick(UArg hTimerSem,
{
Semaphore_pend(timerSem, BIOS_WAIT_FOREVER);
/* Enet_periodicTick should be called from only task context */
+ // printf("[LXC]: EnetMcm_periodicTick enet_mcm.c \n");
Enet_periodicTick(hMcm->hEnet);
}
}
diff --git a/packages/ti/drv/enet/src/mod/cpsw_macport.c b/packages/ti/drv/enet/src/mod/cpsw_macport.c
index 189de4d..120ecf5 100644
--- a/packages/ti/drv/enet/src/mod/cpsw_macport.c
+++ b/packages/ti/drv/enet/src/mod/cpsw_macport.c
@@ -484,6 +484,7 @@ int32_t CpswMacPort_open(EnetMod_Handle hMod,
/* Check if SoC settings (if any) matches the requested MII config */
status = CpswMacPort_checkSocCfg(enetType, instId, macPort, mii);
ENETTRACE_ERR_IF(status != ENET_SOK, "MAC %u: MII mismatch with SoC settings\n", portId);
+ ENETTRACE_ERR_IF(status != ENET_SOK, "[LXC] MAC %u: MII mismatch with SoC settings\n", portId);
/* Soft-reset the Ethernet MAC logic and SGMII port */
if (status == ENET_SOK)
diff --git a/packages/ti/drv/enet/src/phy/enetphy.c b/packages/ti/drv/enet/src/phy/enetphy.c
index 5ac6b11..011c135 100644
--- a/packages/ti/drv/enet/src/phy/enetphy.c
+++ b/packages/ti/drv/enet/src/phy/enetphy.c
@@ -175,7 +175,7 @@ static void EnetPhy_showLinkPartnerCompat(EnetPhy_Handle hPhy,
/* PHY drivers */
extern EnetPhy_Drv gEnetPhyDrvGeneric;
extern EnetPhy_Drv gEnetPhyDrvDp83822;
-extern EnetPhy_Drv gEnetPhyDrvDp83867;
+// extern EnetPhy_Drv gEnetPhyDrvDp83867;
extern EnetPhy_Drv gEnetPhyDrvVsc8514;
/*! \brief All the registered PHY specific drivers. */
@@ -183,7 +183,7 @@ static EnetPhyDrv_Handle gEnetPhyDrvs[] =
{
&gEnetPhyDrvVsc8514, /* VSC8514 */
&gEnetPhyDrvDp83822, /* DP83822 */
- &gEnetPhyDrvDp83867, /* DP83867 */
+ // &gEnetPhyDrvDp83867, /* DP83867 */
&gEnetPhyDrvGeneric, /* Generic PHY - must be last */
};
diff --git a/packages/ti/drv/enet/src/phy/generic_phy.c b/packages/ti/drv/enet/src/phy/generic_phy.c
index 1d3534c..1210ebc 100644
--- a/packages/ti/drv/enet/src/phy/generic_phy.c
+++ b/packages/ti/drv/enet/src/phy/generic_phy.c
@@ -137,48 +137,48 @@ void SetupI2CTransfer(I2C_Handle handle, uint32_t slaveAddr,
printf("\n[LXC]: SetupI2CTransfer end. \n");
}
extern void Board_delay(uint32_t delayCycles);
-void Bcm89881_init(EnetPhy_Handle hPhy)
-{
- I2C_Params i2cParams;
- I2C_Handle handle = NULL;
- uint8_t dataToSlave[4];
-
- /*
- * Configuring TCA6424 IO Exp 2 with addr 0x22
- * This io expander is controlled by i2c0
- */
- /* I2C initialization */
- printf("\n[LXC]: Bcm89881_init start. \n");
- I2C_init();
- I2C_Params_init(&i2cParams);
- i2cParams.transferMode = I2C_MODE_BLOCKING;
- i2cParams.bitRate = I2C_400kHz;
- i2cParams.transferCallbackFxn = NULL;
-
- handle = I2C_open(0U, &i2cParams);
-
-printf("\n[LXC]: Bcm89881_init ing 11111. \n");
- dataToSlave[0] = TCA6424_REG_CONFIG0 | TCA6424_CMD_AUTO_INC;
- dataToSlave[1] = 0x0U;
- SetupI2CTransfer(handle, 0x22, &dataToSlave[0], 2, NULL, 0);
-printf("\n[LXC]: Bcm89881_init ing 22222. \n");
-
- dataToSlave[0] = TCA6424_REG_INPUT0 | TCA6424_CMD_AUTO_INC;
- dataToSlave[1] = 0x0U;
- dataToSlave[2] = 0x0U;
- dataToSlave[3] = 0x0U;
- SetupI2CTransfer(handle, 0x22, &dataToSlave[0], 1, &dataToSlave[1], 3);
-printf("\n[LXC]: Bcm89881_init ing 33333. \n");
-
- /* Set P20 to 0. Delay 22, and Set to 1;
- */
- Board_delay(22);
- dataToSlave[0] = TCA6424_REG_OUTPUT2;
- dataToSlave[1] |= 0x1;
- SetupI2CTransfer(handle, 0x22, &dataToSlave[0], 1, &dataToSlave[1], 1);
- printf("\n[LXC]: Bcm89881_init Stop. \n");
+// void Bcm89881_init(EnetPhy_Handle hPhy)
+// {
+// I2C_Params i2cParams;
+// I2C_Handle handle = NULL;
+// uint8_t dataToSlave[4];
+
+// /*
+// * Configuring TCA6424 IO Exp 2 with addr 0x22
+// * This io expander is controlled by i2c0
+// */
+// /* I2C initialization */
+// printf("\n[LXC]: Bcm89881_init start. \n");
+// I2C_init();
+// I2C_Params_init(&i2cParams);
+// i2cParams.transferMode = I2C_MODE_BLOCKING;
+// i2cParams.bitRate = I2C_400kHz;
+// i2cParams.transferCallbackFxn = NULL;
+
+// handle = I2C_open(0U, &i2cParams);
+
+// printf("\n[LXC]: Bcm89881_init ing 11111. \n");
+// dataToSlave[0] = TCA6424_REG_CONFIG0 | TCA6424_CMD_AUTO_INC;
+// dataToSlave[1] = 0x0U;
+// SetupI2CTransfer(handle, 0x22, &dataToSlave[0], 2, NULL, 0);
+// printf("\n[LXC]: Bcm89881_init ing 22222. \n");
+
+// dataToSlave[0] = TCA6424_REG_INPUT0 | TCA6424_CMD_AUTO_INC;
+// dataToSlave[1] = 0x0U;
+// dataToSlave[2] = 0x0U;
+// dataToSlave[3] = 0x0U;
+// SetupI2CTransfer(handle, 0x22, &dataToSlave[0], 1, &dataToSlave[1], 3);
+// printf("\n[LXC]: Bcm89881_init ing 33333. \n");
+
+// /* Set P20 to 0. Delay 22, and Set to 1;
+// */
+// Board_delay(22);
+// dataToSlave[0] = TCA6424_REG_OUTPUT2;
+// dataToSlave[1] |= 0x1;
+// SetupI2CTransfer(handle, 0x22, &dataToSlave[0], 1, &dataToSlave[1], 1);
+// printf("\n[LXC]: Bcm89881_init Stop. \n");
-}
+// }
static bool GenericPhy_isPhyDevSupported(EnetPhy_Handle hPhy,
const EnetPhy_Version *version)
@@ -601,6 +601,11 @@ static void Bcm89881_config(EnetPhy_Handle hPhy)
printf("[LXC]: Bcm89881_config hPhy->addr = %d\n", hPhy->addr);
+ // g_DEVAD = 0x01;
+ // uint16_t val = 0;
+ // EnetPhy_readReg(hPhy, 0x0002, &val);
+ // printf("[LXC]: Bcm89881_config PMA_PMD_IEEE_DEVICE_ID_REG0 = 0x%x\n", val);
+
/* master mode */
if (g_master) {
if (g_speed == 1000)
diff --git a/packages/ti/drv/enet/unit_test/test_cases/enet_test_entry.c b/packages/ti/drv/enet/unit_test/test_cases/enet_test_entry.c
index 0b065a5..8e62201 100644
--- a/packages/ti/drv/enet/unit_test/test_cases/enet_test_entry.c
+++ b/packages/ti/drv/enet/unit_test/test_cases/enet_test_entry.c
@@ -223,6 +223,7 @@ static void EnetTest_periodicTick(UArg a0,
EnetTestTaskObj *taskObj = (EnetTestTaskObj *)a1;
Enet_periodicTick(EnetTestCommon_getCpswHandle(taskObj));
+ printf("[LXC]: EnetTest_periodicTick enet_test_entry.c \n");
}
}
The ethfw patch:
commit a9710bfbceb112272a918c85cb50db9c3609b99d
Author: liuxianchao <liuxianchao@untouch-tech.com>
Date: Fri Sep 24 10:46:23 2021 +0800
push test code for cpsw9g rgmii5
diff --git a/apps/app_remoteswitchcfg_server/mcu_2_0/main_tirtos.c b/apps/app_remoteswitchcfg_server/mcu_2_0/main_tirtos.c
index 74cc0df..c90e5ac 100644
--- a/apps/app_remoteswitchcfg_server/mcu_2_0/main_tirtos.c
+++ b/apps/app_remoteswitchcfg_server/mcu_2_0/main_tirtos.c
@@ -207,6 +207,14 @@ static void EthApp_startSwInterVlan(char *recvBuff,
static void EthApp_startHwInterVlan(char *recvBuff,
char *sendBuff);
+static int32_t EthApp_addRemoteCoreStaticCfg(Enet_Handle hEnet,
+ uint32_t coreId,
+ uint32_t flowId);
+
+static void EthApp_delRemoteCoreStaticCfg(Enet_Handle hEnet,
+ uint32_t coreId,
+ uint32_t flowId);
+
/* ========================================================================== */
/* Extern variables */
/* ========================================================================== */
@@ -563,6 +571,10 @@ static int32_t EthApp_initEthFw(void)
ethFwCfg.ports[i].portNum);
}
+ /* Set static configuration functions */
+ ethFwCfg.addStaticCfg = &EthApp_addRemoteCoreStaticCfg;
+ ethFwCfg.delStaticCfg = &EthApp_delRemoteCoreStaticCfg;
+
/* Initialize the EthFw */
gEthAppObj.hEthFw = EthFw_init(gEthAppObj.enetType, ðFwCfg);
if (gEthAppObj.hEthFw == NULL)
@@ -571,6 +583,8 @@ static int32_t EthApp_initEthFw(void)
status = ETHAPP_ERROR;
}
+ appLogPrintf("[untouch:liuxianchao]:EthApp_initEthFw do\n");
+
/* Get and print EthFw version */
if (status == ETHAPP_OK)
{
@@ -587,6 +601,168 @@ static int32_t EthApp_initEthFw(void)
return status;
}
+static int32_t EthApp_addMpu10StaticCfg(Enet_Handle hEnet,
+ uint32_t coreId,
+ uint32_t flowId)
+{
+ const uint8_t mcastAddr[ENET_MAC_ADDR_LEN] = {0x01, 0x99, 0xc2, 0x00, 0x01, 0x0E};
+ CpswAle_SetPolicerEntryInArgs polInArgs;
+ CpswAle_SetPolicerEntryOutArgs polOutArgs;
+ CpswAle_SetMcastEntryInArgs mcastInArgs;
+ Enet_IoctlPrms prms;
+ uint32_t entry;
+ int32_t status;
+
+ polInArgs.policerMatch.policerMatchEnMask = 0U;
+
+ /* Add policer entry for port 1 and dstmac */
+ polInArgs.policerMatch.policerMatchEnMask = CPSW_ALE_POLICER_MATCH_PORT;
+ polInArgs.policerMatch.portNum = CPSW_ALE_MACPORT_TO_ALEPORT(ENET_MAC_PORT_2);
+ polInArgs.policerMatch.portIsTrunk = false;
+
+ polInArgs.policerMatch.policerMatchEnMask |= CPSW_ALE_POLICER_MATCH_MACDST;
+ polInArgs.policerMatch.dstMacAddrInfo.portNum = CPSW_ALE_HOST_PORT_NUM;
+ polInArgs.policerMatch.dstMacAddrInfo.addr.vlanId = 0U;
+ EnetUtils_copyMacAddr(&polInArgs.policerMatch.dstMacAddrInfo.addr.addr[0], &mcastAddr[0]);
+
+ polInArgs.threadIdEn = true;
+ polInArgs.threadId = flowId;
+
+ polInArgs.peakRateInBitsPerSec = 0U;
+ polInArgs.commitRateInBitsPerSec = 0U;
+
+ ENET_IOCTL_SET_INOUT_ARGS(&prms, &polInArgs, &polOutArgs);
+
+ appLogPrintf("[yihang:wangkepei]:EthApp_addMpu10StaticCfg do\n");
+
+ status = Enet_ioctl(hEnet, gEthAppObj.coreId, CPSW_ALE_IOCTL_SET_POLICER, &prms);
+ if (status != ENET_SOK)
+ {
+ appLogPrintf("Failed to register PORT1 | MACDST policer: %d\n", status);
+ }
+
+ /* Add policer entry for port 3 and dstmac */
+ if (status == ENET_SOK)
+ {
+ polInArgs.policerMatch.portNum = CPSW_ALE_MACPORT_TO_ALEPORT(ENET_MAC_PORT_5);
+
+ ENET_IOCTL_SET_INOUT_ARGS(&prms, &polInArgs, &polOutArgs);
+
+ status = Enet_ioctl(hEnet, gEthAppObj.coreId, CPSW_ALE_IOCTL_SET_POLICER, &prms);
+ if (status != ENET_SOK)
+ {
+ appLogPrintf("Failed to register PORT3 | MACDST policer: %d\n", status);
+ }
+ }
+
+ /* Add multicast entry with port mask: host port, MAC port 1 and MAC port 3 */
+ if (status == ENET_SOK)
+ {
+ mcastInArgs.addr.vlanId = 0U;
+ EnetUtils_copyMacAddr(&mcastInArgs.addr.addr[0], &mcastAddr[0]);
+
+ mcastInArgs.info.super = false;
+ mcastInArgs.info.fwdState = CPSW_ALE_FWDSTLVL_FWD;
+ mcastInArgs.info.portMask = (CPSW_ALE_HOST_PORT_MASK |
+ CPSW_ALE_MACPORT_TO_PORTMASK(ENET_MAC_PORT_2) |
+ CPSW_ALE_MACPORT_TO_PORTMASK(ENET_MAC_PORT_5));
+ mcastInArgs.info.numIgnBits = 0U;
+
+ ENET_IOCTL_SET_INOUT_ARGS(&prms, &mcastInArgs, &entry);
+
+ status = Enet_ioctl(hEnet, gEthAppObj.coreId, CPSW_ALE_IOCTL_ADD_MCAST, &prms);
+ if (status != ENET_SOK)
+ {
+ appLogPrintf("Failed to add mcast ports: %d\n", status);
+ }
+ }
+
+ return status;
+}
+
+static void EthApp_delMpu10StaticCfg(Enet_Handle hEnet,
+ uint32_t coreId,
+ uint32_t flowId)
+{
+ const uint8_t mcastAddr[ENET_MAC_ADDR_LEN] = {0x01, 0x80, 0xc2, 0x00, 0x01, 0x0E};
+ CpswAle_DelPolicerEntryInArgs polInArgs;
+ Enet_IoctlPrms prms;
+ int32_t status;
+
+ polInArgs.policerMatch.policerMatchEnMask = 0U;
+
+ /* Delete policer entry for port 1 and dstmac */
+ polInArgs.policerMatch.policerMatchEnMask = CPSW_ALE_POLICER_MATCH_PORT;
+ polInArgs.policerMatch.portNum = CPSW_ALE_MACPORT_TO_ALEPORT(ENET_MAC_PORT_2);
+ polInArgs.policerMatch.portIsTrunk = false;
+
+ polInArgs.policerMatch.policerMatchEnMask |= CPSW_ALE_POLICER_MATCH_MACDST;
+ polInArgs.policerMatch.dstMacAddrInfo.portNum = CPSW_ALE_HOST_PORT_NUM;
+ polInArgs.policerMatch.dstMacAddrInfo.addr.vlanId = 0U;
+ EnetUtils_copyMacAddr(&polInArgs.policerMatch.dstMacAddrInfo.addr.addr[0], &mcastAddr[0]);
+
+ polInArgs.aleEntryMask = CPSW_ALE_POLICER_MATCH_PORT;
+
+ ENET_IOCTL_SET_IN_ARGS(&prms, &polInArgs);
+
+ status = Enet_ioctl(hEnet, gEthAppObj.coreId, CPSW_ALE_IOCTL_DEL_POLICER, &prms);
+ if (status != ENET_SOK)
+ {
+ appLogPrintf("Failed to delete PORT1 | MACDST policer: %d\n", status);
+ }
+
+ /* Delete policer entry for port 3 and dstmac */
+ if (status == ENET_SOK)
+ {
+ polInArgs.policerMatch.portNum = CPSW_ALE_MACPORT_TO_ALEPORT(ENET_MAC_PORT_5);
+
+ ENET_IOCTL_SET_IN_ARGS(&prms, &polInArgs);
+
+ status = Enet_ioctl(hEnet, gEthAppObj.coreId, CPSW_ALE_IOCTL_DEL_POLICER, &prms);
+ if (status != ENET_SOK)
+ {
+ appLogPrintf("Failed to delete PORT3 | MACDST policer: %d\n", status);
+ }
+ }
+}
+
+static int32_t EthApp_addRemoteCoreStaticCfg(Enet_Handle hEnet,
+ uint32_t coreId,
+ uint32_t flowId)
+{
+ int32_t status = ENET_SOK;
+
+ switch (coreId)
+ {
+ case IPC_MPU1_0:
+ appLogPrintf("Add static config for mpu1_0\n");
+ status = EthApp_addMpu10StaticCfg(hEnet, coreId, flowId);
+ break;
+
+ default:
+ break;
+ }
+
+ return status;
+}
+
+static void EthApp_delRemoteCoreStaticCfg(Enet_Handle hEnet,
+ uint32_t coreId,
+ uint32_t flowId)
+{
+ switch (coreId)
+ {
+ case IPC_MPU1_0:
+ appLogPrintf("Delete static config for mpu1_0\n");
+ EthApp_delMpu10StaticCfg(hEnet, coreId, flowId);
+ break;
+
+ default:
+ break;
+ }
+}
+
+
static int32_t EthApp_initRemoteServices(void)
{
int32_t status;
diff --git a/ethfw/ethfw.h b/ethfw/ethfw.h
index ef4a8c9..cafab00 100644
--- a/ethfw/ethfw.h
+++ b/ethfw/ethfw.h
@@ -178,6 +178,35 @@ typedef struct EthFw_PortConfig_s
EnetPort_VlanCfg vlanCfg;
} EthFw_Port;
+/*!
+ * \brief Add static configuration.
+ *
+ * Add static configuration that is applicable only to specific remote cores.
+ *
+ * \param hEnet Handle to Enet LLD
+ * \param coreId Remote core's IPC core id
+ * \param flowId Remote core's flow id
+ *
+ * \return 0 if no error. Negative value otherwise.
+ */
+typedef int32_t (*EthFw_addStaticCfg)(Enet_Handle hEnet,
+ uint32_t coreId,
+ uint32_t flowId);
+
+/*!
+ * \brief Delete static configuration.
+ *
+ * Delete static configuration that is applicable only to specific remote cores.
+ *
+ * \param hEnet Handle to Enet LLD
+ * \param coreId Remote core's IPC core id
+ * \param flowId Remote core's flow id
+ */
+typedef void (*EthFw_delStaticCfg)(Enet_Handle hEnet,
+ uint32_t coreId,
+ uint32_t flowId);
+
+
/*!
* \brief Ethernet Firmware configuration
*
@@ -195,6 +224,12 @@ typedef struct EthFw_Config_s
/*! Number of MAC ports owned by EthFw, that is, the size of
* EthFw_Config::ports array */
uint32_t numPorts;
+
+ /* Add static configuration that is applicable only to specific remote cores */
+ EthFw_addStaticCfg addStaticCfg;
+
+ /* Delete static configuration that is applicable only to specific remote cores */
+ EthFw_delStaticCfg delStaticCfg;
} EthFw_Config;
/*!
diff --git a/ethfw/src/ethfw.c b/ethfw/src/ethfw.c
index f8eeb7e..c99b637 100644
--- a/ethfw/src/ethfw.c
+++ b/ethfw/src/ethfw.c
@@ -182,6 +182,12 @@ typedef struct EthFw_Obj_s
/* Handle to PTP stack */
TimeSyncPtp_Handle timeSyncPtp;
+ /* Add static configuration that is applicable only to specific remote cores */
+ EthFw_addStaticCfg addStaticCfg;
+
+ /* Delete static configuration that is applicable only to specific remote cores */
+ EthFw_delStaticCfg delStaticCfg;
+
} EthFw_Obj;
/* ========================================================================== */
@@ -268,6 +274,10 @@ void EthFw_initConfigParams(Enet_Type enetType,
CpswHostPort_Cfg *hostPortCfg = &cpswCfg->hostPortCfg;
EnetRm_ResCfg *resCfg = &cpswCfg->resCfg;
+ /* Initialize Static config function pointers */
+ config->addStaticCfg = NULL;
+ config->delStaticCfg = NULL;
+
/* MAC port ownership */
config->ports = NULL;
config->numPorts = 0U;
@@ -306,6 +316,10 @@ EthFw_Handle EthFw_init(Enet_Type enetType,
memset(&gEthFwObj, 0, sizeof(gEthFwObj));
+ /* Save static config function pointers */
+ gEthFwObj.addStaticCfg = config->addStaticCfg;
+ gEthFwObj.delStaticCfg = config->delStaticCfg;
+
/* Save config parameters */
gEthFwObj.cpswCfg = config->cpswCfg;
gEthFwObj.numPorts = config->numPorts;
@@ -419,6 +433,10 @@ int32_t EthFw_initRemoteConfig(EthFw_Handle hEthFw)
cfg.notifyServiceRemoteCoreId[0] = IPC_MPU1_0;
cfg.notifyServiceRemoteCoreId[1] = IPC_MCU2_1;
+ /* Static configuration callbacks */
+ cfg.addStaticCfg = gEthFwObj.addStaticCfg;
+ cfg.delStaticCfg = gEthFwObj.delStaticCfg;
+
status = CpswProxyServer_init(&cfg);
if (status != ENET_SOK)
{
@@ -558,6 +576,9 @@ static void EthFw_initLinkArgs(EnetPer_PortLinkCfg *linkArgs,
if (gEthFwObj.ports[i].portNum == macPort)
{
macCfg->vlanCfg = gEthFwObj.ports[i].vlanCfg;
+
+ appLogPrintf("[untouch:liuxianchao] EthFw_initLinkArgs, macPort = %d, vlanCfg portCfi is %d, portPri is %d, portVID is %d\r\n\n",
+ macPort, macCfg->vlanCfg.portCfi, macCfg->vlanCfg.portPri, macCfg->vlanCfg.portVID);
}
}
}
diff --git a/ethremotecfg/server/include/cpsw_proxy_server.h b/ethremotecfg/server/include/cpsw_proxy_server.h
index c1acfa9..f4d2e41 100644
--- a/ethremotecfg/server/include/cpsw_proxy_server.h
+++ b/ethremotecfg/server/include/cpsw_proxy_server.h
@@ -162,6 +162,35 @@ typedef struct CpswProxyServer_RemoteCoreConfig_s
char serverName[ETHREMOTECFG_SERVER_MAX_NAME_LEN];
} CpswProxyServer_RemoteCoreConfig;
+/*!
+ * \brief Add static configuration.
+ *
+ * Add static configuration that is applicable only to specific remote cores.
+ *
+ * \param hEnet Handle to Enet LLD
+ * \param coreId Remote core's IPC core id
+ * \param flowId Remote core's flow id
+ *
+ * \return 0 if no error. Negative value otherwise.
+ */
+typedef int32_t (*CpswProxyServer_addStaticCfg)(Enet_Handle hEnet,
+ uint32_t coreId,
+ uint32_t flowId);
+
+/*!
+ * \brief Delete static configuration.
+ *
+ * Delete static configuration that is applicable only to specific remote cores.
+ *
+ * \param hEnet Handle to Enet LLD
+ * \param coreId Remote core's IPC core id
+ * \param flowId Remote core's flow id
+ */
+typedef void (*CpswProxyServer_delStaticCfg)(Enet_Handle hEnet,
+ uint32_t coreId,
+ uint32_t flowId);
+
+
/*!
* \brief Cpsw Proxy Server Remote Configuration structure
*
@@ -199,6 +228,12 @@ typedef struct CpswProxyServer_Config_s
/*! Remote Core configuration */
CpswProxyServer_RemoteCoreConfig remoteCoreCfg[ETHREMOTECFG_SERVER_MAX_INSTANCES];
+
+ /* Add static configuration that is applicable only to specific remote cores */
+ CpswProxyServer_addStaticCfg addStaticCfg;
+
+ /* Delete static configuration that is applicable only to specific remote cores */
+ CpswProxyServer_delStaticCfg delStaticCfg;
} CpswProxyServer_Config_t;
/*!
diff --git a/ethremotecfg/server/src/cpsw_proxy_server.c b/ethremotecfg/server/src/cpsw_proxy_server.c
index 4c01eaa..295b781 100644
--- a/ethremotecfg/server/src/cpsw_proxy_server.c
+++ b/ethremotecfg/server/src/cpsw_proxy_server.c
@@ -184,6 +184,12 @@ typedef struct CpswProxyServer_Obj_s
SemaphoreP_Handle rdevStartSem;
CpswProxyServer_EthDriverObj ethDrvObj;
CpswProxyServer_NotifyServiceObj notifyServiceObj;
+
+ /* Add static configuration that is applicable only to specific remote cores */
+ CpswProxyServer_addStaticCfg addStaticCfg;
+
+ /* Delete static configuration that is applicable only to specific remote cores */
+ CpswProxyServer_delStaticCfg delStaticCfg;
} CpswProxyServer_Obj;
/* ========================================================================== */
@@ -592,10 +598,13 @@ static int32_t CpswProxyServer_registerMacHandlerCb(uint32_t host_id,
u8 *mac_address,
uint32_t flow_idx)
{
+ CpswProxyServer_Obj *hProxyServer;
int32_t status;
Enet_Handle hEnet = (Enet_Handle)((uintptr_t)handle);
uint32_t start_flow_idx, flow_idx_offset;
+ hProxyServer = CpswProxyServer_getHandle();
+
CpswProxyServer_validateHandle(hEnet);
EnetAppUtils_absFlowIdx2FlowIdxOffset(hEnet, host_id, flow_idx, &start_flow_idx, &flow_idx_offset);
appLogPrintf("Function:%s,HostId:%u,Handle:%p,CoreKey:%x, MacAddress:%x:%x:%x:%x:%x:%x, FlowIdx:%u, FlowIdxOffset:%u\n",
@@ -618,6 +627,23 @@ static int32_t CpswProxyServer_registerMacHandlerCb(uint32_t host_id,
appLogPrintf("EnetAppUtils_regDstMacRxFlow() failed CPSW_ALE_IOCTL_SET_POLICER: %d\n", status);
status = RPMSG_KDRV_TP_ETHSWITCH_CMDSTATUS_EFAIL;
}
+
+ if (ENET_SOK == status)
+ {
+ if (hProxyServer->addStaticCfg != NULL)
+ {
+ status = hProxyServer->addStaticCfg(hEnet, host_id, flow_idx_offset);
+ if (ENET_SOK != status)
+ {
+ appLogPrintf("Failed to add static config for coreId=%u: %d\n", host_id, status);
+ }
+ }
+ }
+
+ if (status != ENET_SOK)
+ {
+ status = RPMSG_KDRV_TP_ETHSWITCH_CMDSTATUS_EFAIL;
+ }
else
{
status = RPMSG_KDRV_TP_ETHSWITCH_CMDSTATUS_OK;
@@ -632,10 +658,13 @@ static int32_t CpswProxyServer_unregisterMacHandlerCb(uint32_t host_id,
u8 *mac_address,
uint32_t flow_idx)
{
+ CpswProxyServer_Obj *hProxyServer;
int32_t status;
Enet_Handle hEnet = (Enet_Handle)((uintptr_t)handle);
uint32_t start_flow_idx, flow_idx_offset;
+ hProxyServer = CpswProxyServer_getHandle();
+
CpswProxyServer_validateHandle(hEnet);
EnetAppUtils_absFlowIdx2FlowIdxOffset(hEnet, host_id, flow_idx, &start_flow_idx, &flow_idx_offset);
appLogPrintf("Function:%s,HostId:%u,Handle:%p,CoreKey:%x, MacAddress:%x:%x:%x:%x:%x:%x, FlowIdx:%u, FlowIdOffset:%u\n",
@@ -653,6 +682,19 @@ static int32_t CpswProxyServer_unregisterMacHandlerCb(uint32_t host_id,
flow_idx_offset);
status = EnetAppUtils_unregDstMacRxFlow(hEnet, core_key, host_id, start_flow_idx, flow_idx_offset, mac_address);
+ if (status != ENET_SOK)
+ {
+ appLogPrintf("Failed EnetAppUtils_unregDstMacRxFlow: %d\n", status);
+ }
+
+ if (ENET_SOK == status)
+ {
+ if (hProxyServer->delStaticCfg != NULL)
+ {
+ hProxyServer->delStaticCfg(hEnet, host_id, flow_idx_offset);
+ }
+ }
+
if (status != ENET_SOK)
{
appLogPrintf("Failed EnetAppUtils_unregDstMacRxFlow: %d\n", status);
@@ -1657,6 +1699,10 @@ int32_t CpswProxyServer_init(CpswProxyServer_Config_t *cfg)
hProxyServer->initDone = true;
appLogPrintf("Remote demo device (core : mcu2_0) .....\r\n");
+
+ hProxyServer->addStaticCfg = cfg->addStaticCfg;
+ hProxyServer->delStaticCfg = cfg->delStaticCfg;
+
return ENET_SOK;
}
