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AM3358: Burst Read / Burst Write setting

Conor
Guru 14240 points

Part Number: AM3358

Hi,

I have a question about what happens when I enable the WRAPBURST field in the GPMC_CONFIG1_x register.

Is it okay to recognize that when reading and writing data to consecutive addresses, it will be Burst Read/Burst Write?

Thanks,

KT

  • 0
    TI__Mastermind 30470 points

    Hi KT,

    WRAPBURST
    Enables the wrapping burst capability
    Must be set if the attached device is configured in wrapping burst
    0h = Synchronous wrapping burst not supported
    1h = Synchronous wrapping burst supported

    WRAPBURST It is involved with synchronous reads from a memory that supports Burst Wrap.
    If GPMC starts reading from an address that is not a multiple of the burst length...
    With WRAPBURST enabled, after the last data in a row of data is read, the first data in the same row is expected.
    With WRAPBURST disabled, after the last data in a row of data is read, the next row is accessed and first data from the new row is read. This might require a delay indicated by the WAIT pin.

    2 examples:
    Read from Addr0 - burst 4 words:
    - WRAPBUST enabled: 0123
    - WRAPBURST disabled: 0123 (same)
    Read from Addr1 - burst of 4 words:
    - WRAPBUST enabled: 1230
    - WRAPBURST disabled: 1234 (different)

    Refer to a datasheet of a device that supports Burst Wrap like the P30 NOR Flash:
    media.digikey.com/.../P30 StrataFlash Embedded Memory DS.pdf
    See 11.2.6 Burst Sequence

    =-=-

    Maybe you just want to enable Burst mode?
    To enable burst, you must set ATTACHEDDEVICEPAGELENGTH + READMULTIPLE and/or WRITEMULTIPLE bit fields in the same GPMC_CONFIG1_n register.

    GPMC cannot burst with asynch write. It must be synchronous (GPMC_CLK edge latches data).
    CPU access can achieve burst of 2x 16-bit words. DMA is required for larger bursts.

    Hope this helps,
    Mark