TIDEP-01020: Transmission Line Impedance of LPDDR4 wires

Junpei Kishi

Part Number: TIDEP-01020
Other Parts Discussed in Thread: DRA829V,

Hi experts,

I'm referring to TIDEP-01020 in order to design a PCB using DRA829V my own.

Could you let me know how much the line impedance between LPDDR4 and SoC in 8 layers design?
I think it's depends on whether the wire is single ended or paired, so please let me know each.

Additionally, some wires are designed using only single layers, but I wonder that these signal meet the impedance to other signals which uses multiple layers.
Could you tell me that all signal wires are compatible in impedance or not?

Thanks and Best Regards,
Junpei

over 2 years ago

+1 Robert Eschler over 2 years ago

TI__Mastermind 43910 points

The PCB layer plot file for the design (TIDM633.zip) located on TI.com includes all the PCB stack-up information, including material, spacing, and all the line impedances for each layer.

https://www.ti.com/lit/zip/tidm633

0 Junpei Kishi over 2 years ago in reply to Robert Eschler

TI__Intellectual 865 points

Hi Robert,

Thanks for your information!

Regards,
Junpei Kishi

0 Junpei Kishi over 2 years ago in reply to Junpei Kishi

TI__Intellectual 865 points

Hi Robert,

Please let me ask one more question regarding to this.

Around SoC and DRAM IC, it looks like that there are not under impedance controlled.
I think it is because of BGA fanout, but how do you choose the width of each signals for CS/CKE/DQ/CA?

Regards,
Junpei

0 Robert Eschler over 2 years ago in reply to Junpei Kishi

TI__Mastermind 43910 points

Goal is always to get trace width as close to target impedance as possible - even in BGA breakout areas. Sometimes compromises have to be make, but try to keep impedance difference minimal, and keep trace segment as short as possible. Simulations will help identify if the impedance is off too much or if the trace segment with the different impedance is too long.

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TIDEP-01020: Transmission Line Impedance of LPDDR4 wires