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DRA821U: Download Jacinto7 J7200 (DRA821) EVM

Part Number: DRA821U
Other Parts Discussed in Thread: DRA821

Thank you for your cooperation.
Now, I am selecting the CPU for the next product, and I am evaluating the A72 core performance of the DRA821U (mainly the execution / access speed with and without the SRAM and DDR cache).
However, I am in trouble because I cannot build a debug environment.

The H / W used is as follows.
- Jacinto7 J7200 (DRA821) EVM
J7200 system on module (SOM) board
Jacinto7Common Processor Board (CPB)
Set to Noboot mode.
The S / W used is as follows.
- CCS10.4.0.00006_win64
- ti-processor-sdk-rtos-j7200-evm-08_00_00_12
- ti-processor-sdk-rtos-j7200-evm-08_00_00_12-windows_codegen_tools
procedure
- Install CCS with "TDAx Driver Assistance SoC and Jacinto DRAx Infotainment SoC" check.
- Connect the CCS target configuration with "Board on Device" = "Texas Instruments XDS110 USB debug probe".
- Select the "EVM_J7200" board.(Because there is no Jacinto7 VCL)
- Load ".. \ .. \ emulation \ gel \ J7200_DRA821 \ J7VCL_SI.gel" into DMSC_Cortex_M3_0 on the [Detailed Settings] tab of the target configuration file.
- Edit the launch.js script according to the environment.(Attachment)
- Start the target configuration with "Launch Selected Configuration" of the target configuration.
Question 1
When the launch.js script is loaded with the loadSciserverFlag set to 1, the following error occurs.
"Error evaluating" GEL_Load (" C: /TI/pdk_j7200_08_00_00_37/packages/ti/drv/sciclient/tools/ccsLoadDmsc/j7200/sciserver_testapp_mcu1_0_release.xer5f") ": Encountered a problem loading file: C: / TI / pdk_j7ti / drv / sciclient / tools / ccsLoadDmsc / j7200 / sciserver_testapp_mcu1_0_release.xer5f "
Looking at the folder, there is a 0-byte sciserver_testapp_mcu1_0_release.xer5f.
What is the cause?
Is it necessary to set loadSciserverFlag to 1 in order to evaluate the A72 core?
Problem 2
When loadSciserverFlag is set to 0, the launch.js script will be loaded normally, but the program cannot be loaded even if both CortexA72_0_0 and CortexA72_0_1 are connected targets.
Is this the cause of Problem 1?
Or is there another problem?

Thank you.