The LPDDR4 chosen by the TDA4VM SOC is K4FBE3D4HMTFCL from SASUNGM. And here's a question:
a. The customer uses a 10-layer board design and DDR section references a 16-layer board design to route the wire;
b. The LPDDR4 CLK is a T-trace with a differential controlled by 70 ohms;
c. For the T section, 140 ohm impedance, cannot be achieved, and the customer's current practice is not to do impedance control.
Issue: what or what considerations should take into account when debugging?
Thanks a lot!
Best Regards,
Cherry Zhou
