I used the DDR module of the microcontroller (C6748) and created the software to access the SDRAM (IS43DR16640C-25DBLI).
For a while after launching the software, the software can access (Read / Write) the SDRAM as intended. However, about 1 to 2 hours after starting to operate the microcomputer, the data read from SDRAM sometimes had an unintended value.
Is the SDRAM initialized properly?
The function prepared to initialize SDRAM (executed only once when the software is started) and related constants are attached below.
If you have any additional information you need, please let me know.
Thank you.
/*------------------------------------------------------------------------------
*[Description]
* This function initializes DDR registers.
*[Arguments]
* void
*[Return]
* void
*------------------------------------------------------------------------------*/
static void McuC_InitializeDdrRegister(void)
{
uint32_t readyBit; /* READY bit in VTPIO_CTL register */
uint32_t gostatBit; /* GOSTAT bit in PTSTAT register */
/* Initializes DDR register in accordance with section 13.2.13.1 of TMS320C6748 Technical Reference Manual */
/* Sequence 1-1 (Performed by "McuC_InitializeSysconRegister" function.) */
/* Sequence 1-2 (Performed by "McuC_InitializePllcRegister" function.) */
/* Sequence 2 (Performed by "McuC_InitializePscRegister" function.) */
/* Sequence 3 */
*(volatile uint32_t*)(SYSCFG1_ADDRESS + SYSCFG1_VTPIO_CTL) &= (~VTPIO_POWERDN);
*(volatile uint32_t*)(SYSCFG1_ADDRESS + SYSCFG1_VTPIO_CTL) &= (~VTPIO_LOCK);
*(volatile uint32_t*)(SYSCFG1_ADDRESS + SYSCFG1_VTPIO_CTL) |= (VTPIO_CLKRZ);
*(volatile uint32_t*)(SYSCFG1_ADDRESS + SYSCFG1_VTPIO_CTL) &= (~VTPIO_CLKRZ);
*(volatile uint32_t*)(SYSCFG1_ADDRESS + SYSCFG1_VTPIO_CTL) |= (VTPIO_CLKRZ);
WAIT_CLOCK(MS_TO_CLOCK(10U));
do
{
readyBit = *(volatile uint32_t*)(SYSCFG1_ADDRESS + SYSCFG1_VTPIO_CTL);
readyBit &= VTPIO_READY;
}while(readyBit == 0U);
*(volatile uint32_t*)(SYSCFG1_ADDRESS + SYSCFG1_VTPIO_CTL) |= (VTPIO_LOCK);
*(volatile uint32_t*)(SYSCFG1_ADDRESS + SYSCFG1_VTPIO_CTL) |= (VTPIO_POWERDN);
/* Sequence 4 */
*(volatile uint32_t*)(SYSCFG1_ADDRESS + SYSCFG1_VTPIO_CTL) |= (VTPIO_IOPWRDN);
/* Sequence 5 */
*(volatile uint32_t*)(DDR_ADDRESS + DDR_DRPYC1R) |= (DDR_EXT_STRBEN);
*(volatile uint32_t*)(DDR_ADDRESS + DDR_DRPYC1R) |= (DDR_PWRDNEN);
*(volatile uint32_t*)(DDR_ADDRESS + DDR_DRPYC1R) &= (~DDR_RL);
*(volatile uint32_t*)(DDR_ADDRESS + DDR_DRPYC1R) |= DDR_INIT_REGISTER_DATA[DDR_INIT_DRPYC1R];
/* Sequence 6 */
*(volatile uint32_t*)(SYSCFG1_ADDRESS + SYSCFG1_DDR_SLEW) &= (~SLEW_DDR_PDENA);
*(volatile uint32_t*)(SYSCFG1_ADDRESS + SYSCFG1_DDR_SLEW) &= (~SLEW_CMOSEN);
/* Sequence 7 */
*(volatile uint32_t*)(DDR_ADDRESS + DDR_SDCR) |= (DDR_BOOTUNLOCK);
/* Sequence 8 */
*(volatile uint32_t*)(DDR_ADDRESS + DDR_SDCR) = DDR_INIT_REGISTER_DATA[DDR_INIT_SDCR];
/* Sequence 9 (Unnecessary) */
/* Sequence 10 */
*(volatile uint32_t*)(DDR_ADDRESS + DDR_SDTIMR1) = DDR_INIT_REGISTER_DATA[DDR_INIT_SDTIMR1];
*(volatile uint32_t*)(DDR_ADDRESS + DDR_SDTIMR2) = DDR_INIT_REGISTER_DATA[DDR_INIT_SDTIMR2];
/* Sequence 11 */
*(volatile uint32_t*)(DDR_ADDRESS + DDR_SDCR) &= (~DDR_TIMUNLOCK);
/* Sequence 12 */
*(volatile uint32_t*)(DDR_ADDRESS + DDR_SDRCR) |= (DDR_LPMODEN);
*(volatile uint32_t*)(DDR_ADDRESS + DDR_SDRCR) |= (DDR_MCLKSTOPEN);
*(volatile uint32_t*)(DDR_ADDRESS + DDR_SDRCR) &= (~DDR_SR_PD);
*(volatile uint32_t*)(DDR_ADDRESS + DDR_SDRCR) &= (~DDR_RR);
*(volatile uint32_t*)(DDR_ADDRESS + DDR_SDRCR) = DDR_INIT_REGISTER_DATA[DDR_INIT_SDRCR];
/* Sequence 13 */
*(volatile uint32_t*)PSC_INIT_REGISTER_ADDRESS[PSC_MOD_DDR2_mDDR] = PSC_STATE_SYNC_RESET;
*(volatile uint32_t*)(PSC1_ADDRESS + PSCX_PTCMD) |= PSC_GO;
WAIT_CLOCK(MS_TO_CLOCK(10U));
do
{
gostatBit = *(volatile uint32_t*)(PSC1_ADDRESS + PSCX_PTSTAT);
gostatBit &= PSC_GOSTAT;
}while(gostatBit != 0U);
/* Sequence 14 */
*(volatile uint32_t*)PSC_INIT_REGISTER_ADDRESS[PSC_MOD_DDR2_mDDR] = PSC_STATE_ENABLE;
*(volatile uint32_t*)(PSC1_ADDRESS + PSCX_PTCMD) |= PSC_GO;
WAIT_CLOCK(MS_TO_CLOCK(10U));
do
{
gostatBit = *(volatile uint32_t*)(PSC1_ADDRESS + PSCX_PTSTAT);
gostatBit &= PSC_GOSTAT;
}while(gostatBit != 0U);
/* Sequence 15 */
*(volatile uint32_t*)(DDR_ADDRESS + DDR_SDRCR) &= (~DDR_LPMODEN);
*(volatile uint32_t*)(DDR_ADDRESS + DDR_SDRCR) &= (~DDR_MCLKSTOPEN);
/* Sequence 16 */
*(volatile uint32_t*)(DDR_ADDRESS + DDR_PBBPR) = DDR_INIT_REGISTER_DATA[DDR_INIT_PBBPR];
return;
}
/*--------<Register Data>-----------------------------------------------------*/
/* Register Start Address */
#define DDR_ADDRESS (0xB0000000U)
/* Registers Offset Address */
#define DDR_REVID (0x00U) /* Revision ID Register */
#define DDR_SDRSTAT (0x04U) /* SDRAM Status Register */
#define DDR_SDCR (0x08U) /* SDRAM Configuration Register */
#define DDR_SDRCR (0x0CU) /* SDRAM Refresh Control Register */
#define DDR_SDTIMR1 (0x10U) /* SDRAM Timing Register 1 */
#define DDR_SDTIMR2 (0x14U) /* SDRAM Timing Register 2 */
#define DDR_SDCR2 (0x1CU) /* SDRAM Configuration Register 2 */
#define DDR_PBBPR (0x20U) /* Peripheral Bus Burst Priority Register */
#define DDR_PC1 (0x40U) /* Performance Counter 1 Registers */
#define DDR_PC2 (0x44U) /* Performance Counter 2 Register */
#define DDR_PCC (0x48U) /* Performance Counter Configuration Register */
#define DDR_PCMRS (0x4CU) /* Performance Counter Master Region Select Register */
#define DDR_PCT (0x50U) /* Performance Counter Time Register */
#define DDR_IRR (0xC0U) /* Interrupt Raw Register */
#define DDR_IMR (0xC4U) /* Interrupt Mask Register */
#define DDR_IMSR (0xC8U) /* Interrupt Mask Set Register */
#define DDR_IMCR (0xCCU) /* Interrupt Mask Clear Register */
#define DDR_DRPYC1R (0xE4U) /* DDR PHY Control Register 1 */
#define DDR_EXT_STRBEN (0x00000080U) /* See DRPYC1R register. */
#define DDR_PWRDNEN (0x00000040U) /* See DRPYC1R register. */
#define DDR_RL (0x00000007U) /* See DRPYC1R register. */
#define DDR_BOOTUNLOCK (0x00800000U) /* See SDCR register. */
#define DDR_TIMUNLOCK (0x00008000U) /* See SDCR register. */
#define DDR_PAGESIZE_IBANK_CL (0x00000FFFU) /* See SDCR register. */
#define DDR_RR (0x0000FFFFU) /* See SDRCR register. */
#define DDR_LPMODEN (0x80000000U) /* See SDRCR register. */
#define DDR_MCLKSTOPEN (0x40000000U) /* See SDRCR register. */
#define DDR_SR_PD (0x00800000U) /* See SDRCR register. */
#define DDR_MEMORY_START_ADDRESS (0xC0000000U)
#define DDR_CLOCK (150.0) /*[MHz]*/
#define DDR_REFRESH_RATE (7.8) /*[us]*/
/*--------<Initializaton Data>-----------------------------------------------*/
/* Initialization Index */
enum DDR_INIT_INDEX
{
DDR_INIT_DRPYC1R,
DDR_INIT_SDCR,
DDR_INIT_SDTIMR1,
DDR_INIT_SDTIMR2,
DDR_INIT_SDRCR,
DDR_INIT_PBBPR,
DDR_INIT_COUNT,
};
/* Initialization Register Data */
static const uint32_t DDR_INIT_REGISTER_DATA[DDR_INIT_COUNT] =
{
[DDR_INIT_DRPYC1R] = 0x00000006U,
/* - Read latency; 6(minimum)
*/
[DDR_INIT_SDCR] = 0x0013CA32U,
/* - DDR2 termination resistor; Disabled
* - Internal Bank position; Normal addressing
* - DDR type; DDR2(SDRAMEN = 1, MSDRAMEN = 0, DDREN = 1, DDR2EN = 1)
* - DLL; Enabled
* - Timing unlock; Unlocked
* - SDRAM data bus width; 16bit
* - CAS; CAS Latency = 5
* - Internal SDRAM bank; 8 banks
* - Page Size; 10 column address bits
*/
[DDR_INIT_SDTIMR1] = 0xFFFFFFFFU,
/* - T_RFC; 127.5ns
* - T_RP ; 12.5ns
* - T_RCD; 12.5ns
* - T_WR ; 15.0ns
* - T_RAS; 40.0ns
* - T_RC ; 55.0ns
* - T_RRD; 10.0ns
* - T_WTR; 10.0ns
*/
[DDR_INIT_SDTIMR2] = 0xFFFFFFFFU,
/* - T_RASMAX; 70.0ns
* - T_XP ; 2.0ns
* - T_ODT ; 1 (CL(3) - tAOND(2))
* - T_XSNR ; 137.5ns
* - T_XSRD ; 200.0ns
* - T_RTP ; 7.5ns
* - T_CKE ; 3.0ns
*/
[DDR_INIT_SDRCR] = 0xC0000000U|((uint32_t)(DDR_REFRESH_RATE*DDR_CLOCK)),
/* - Low-power mode; Disabled
* - MCLK stop; Disabled
* - Self-refresh mode; Enabled
* - Refresh rate; 7.8us (7.8us * 150MHz = 1170 = 0x492)
*/
[DDR_INIT_PBBPR] = 0x00000030U,
/* - Priority raise old counter; Recommended setting
*/
};
