This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

DRA821U: [Lauterbach debug] how to pause OS timer when break debug, and resume OS timer when continue debug?

Part Number: DRA821U
Other Parts Discussed in Thread: DRA821

Dear Ti expert,

When we debug the code on the R5F core with Lauterbach debugger, the OS would work abnormally once we break the debug. We thought that would caused by the OS timer which wouldn't pause at the time we break the debug. So we tried to pause the timer manually with command when we break the debug. 

The lauterbach debugger supports command group which allows to define a sequence of read/write accesses that are automatically performed directly after the program execution has halted (manual break, breakpoint or end of single step) or before program execution is continued with Go or Step. 

We use this command to write the timer control register to stop the timer when we halt the debug and  resume the timer when we continue the debug. The test results show that the timer can be stopped and resumed as expected,  but the OS still runs into ErrorHook. In our opinion, this is because that stopping the timer with command takes a few milliseconds which would lead to the OS runs abnormally.

Base on the results above, we have some questions here :

1.If there is a debug mode which would entry automatically when we connect the debugger and would halt/resume the timer automatically when we debug the code step by step?  If the debug mode exists, how to enable it? 
2.If the debug mode doesn't exist, if there is a hardware mechanism or other methods which could pause/resume the timer when debug the code ? 
3.If the Cross Trigger Interface would be helpful to this issue? 

  • Hello Ji,

    You can use the hardware's debug suspend router to pause and restart a timer along with the core. I have uploaded some example scripts I used with the DRA821.  If your company has CDDS access, you might look for these scripts in the DRA821 area as I periodically update them there. Take a look at the example in ./cmm-dra821/notes/suspend-mapping.txt.

    /cfs-file/__key/communityserver-discussions-components-files/791/cmm_2D00_dra821.7z

    As seen in the example you can set the mcu_timer0's state to follow the debug mode of the MCU-R50 by executing the following statement on the command line or from a CMM:

         Data.Set AXI:0x4C:0x3D300168 %LE %Long (0x10000|17.

    Regards,

    Richard W.

  • Hello Expert, 
    Thanks for your reply. I tried the method you supplied and it really works.  So I want to know if you could please provide some technical reference about the hardware's debug suspend router that you mentioned ? Because I couldn't found any information about it on the J7200 DRA821 technical reference manual.

    I tried your method on the Lauterbach debugger. And how about the CCS debugger ?  

    Best Regards

  • Hello Ji,

    Thanks for feeding back your results. Glad it worked for you as expected. The DRA821 TRM section for debug is not complete. Typically the TRMs debug chapter provides a summary of features as users typically interact with these components via a debug tool, like CCS or TRACE32. I will attach the data which will be in the TRM and mapping data so you can see what all devices can be suspended.

    The suspend router functionality has been in TI chips for many years (>15).  For CCS (and TRACE32/Lauterbach) typically the setup is part of GEL (or CMM) scripts provided by vendors. The router has a dual address mapping, one map is accessed via the main system bus and the other is via the debug configuration bus.  In Lauterbach accesses can be done directly using address space identifiers from multiple perspectives.  In CCS you can program these by connecting to the hidden DAP target, or by using a CPU which can read/write into the system address space.  For DRA821, I have only personally used this feature from TRACE32 but there is no reason you cannot achieve the same using CCS or another tool given the addresses provided in the examples.

    /cfs-file/__key/communityserver-discussions-components-files/791/dra821_5F00_suspend_5F00_router.pdf

    Regards,
    Richard W.

  • Dear Expert,

    Thanks for your reply. I have learned the pdf that you provide. But there is no information about the register of the debug suspend router(DBGSUSP_RTR). Could you please provide more information about it.? And if you could provide a gel script or others which could run on the CCS debugger?  Because I don't know how to transform the .cmm file to .gel file, like the code you provide :

    Data.Set EAPB:0x9d300168 %LE %Long (0x10000 | 17.)

    Data.Set EAPB:0x9d30011C %LE %Long (0x10000 | 19.)

    Data.Set EAPB:0x9d300120 %LE %Long (0x10000 | 20.)

    Could you please  transform them into the format which could run on the CCS debuger.

    Thanks a lot .

    Best Regards.

  • Hello Ji,

    The suspend controller is an array of 32-bit mux control registers. There is a mux-register per controllable peripheral. Each suspend mux-register allows reading/writing to the lower bits 4:0 with a value of an initiator/core to link to a peripherals suspend function.  Bit16 in each register is the enable-override function which is the enable/disable gate for the value written into bits 4:0. The reset of the bit fields are reserved. 

    For CCS to program the suspend router mux-register it must write using the debuggers private APB bus or by using the system views TRM address. To do this in CCS, a connection to the hidden DAP target needs to be made. From here a GEL associated with the DAP can access write the correct address directly or the memory browser can be used.

    I will attach a snap shot marking up the connection points for CCS and a video of executing accesses to this region via both methods.  With this you can get the functionality working with CCS like you have today with Lauterbach.

    Regards,
    Richard W.