synchronous EMIF read on DM365

Alexander Khvilivitzky

I'm trying to test EMIF sync read mode on the EVMDM365 board. I'm monitoring EMIF signals with a scope on J14 header. I want to reproduce the waveform shown on Fig.6-17 of the DM365 data sheet (sprs457d).

I am setting AEMIF_ONENANDCTL to 0x433 (my intention is to enable synchronous mode on both chip selects).

I'm setting AEMIF_NANDFCR to 0 (my understanding is that OneNAND and NAND modes are mutually exclusive).

Then I try a memcpy() from address 0x02000000. If I copy 1 to 3 bytes, the cycle occurs as expected. If I try to copy 4 bytes or more, the EM_CE0 goes low, but the cycle never ends. The board stops responding.

Is there some setting that I'm missing? What's the proper way of setting a synchronous read mode on the EMIF?

over 14 years ago

0 Alexander Khvilivitzky over 14 years ago

Expert 1055 points

Made it work by setting bus width to 2 bytes in AEMIF_A1CR and AEMIF_A2CR.

Still have a question: the maximum burst length I can achieve (using DMA or memcpy) is 32 bytes (16 clocks + read latency + 1 clock for EM_ADV). Any way to increase that?

0 Alexander Khvilivitzky over 14 years ago in reply to Alexander Khvilivitzky

Expert 1055 points

Still waiting for an answer on max EMIF burst length in synchronous mode - is it limited to 32 bytes or could be increased? Does it work the same way with OneNAND?

0 Marcus Cooksey over 14 years ago in reply to Alexander Khvilivitzky

TI__Genius 9510 points

Alexander,

I will forward this question to one of our experts in this area.

0 Alexander Khvilivitzky over 14 years ago in reply to Marcus Cooksey

Expert 1055 points

Marcus,

any response from the experts yet?

Thanks,

Alexander.

0 Marcus Cooksey over 14 years ago in reply to Alexander Khvilivitzky

TI__Genius 9510 points

Sorry for the long delay. I hope to have an expert post a response soon.

0 Marcus Cooksey over 14 years ago in reply to Marcus Cooksey

TI__Genius 9510 points

It seems that higher bust can be supported using the EDMA. Please see the following thread.

http://e2e.ti.com/support/dsp/davinci_digital_media_processors/f/100/t/66899.aspx

0 Alexander Khvilivitzky over 14 years ago in reply to Marcus Cooksey

Expert 1055 points

Marcus,

thanks for an interesting link.

My results however show that even when EDMA is used the large transfer (I set it to 1024 bytes in EDMA PaRAM block) is split into separate 32-byte bursts. Tai mentioned something about the bridges:

"The bridges will break the transfer up if it has to, but that’s dependent on source and destination of the data path."

In my case the destination is DDR, could it be the reason? I'm trying to figure out the way to further improve the speed.

0 Marcus Cooksey over 14 years ago in reply to Alexander Khvilivitzky

TI__Genius 9510 points

Can you specify what your edma A-COUNT, B-COUNT, and C-COUNT values are set to?

0 Alexander Khvilivitzky over 14 years ago in reply to Marcus Cooksey

Expert 1055 points

Here's a relevant part of my code (.sysmem > DDR2 in the linker file):

typedef struct {
Uint32 opt;
Uint32 src;
Uint16 acnt;
Uint16 bcnt;
Uint32 dst;
Uint16 srcbidx;
Uint16 dstbidx;
Uint16 link;
Uint16 bcntrld;
Uint16 srccidx;
Uint16 dstcidx;
Uint16 ccnt;
Uint16 res;
} PARAMSET;

#define BUF_SIZE 1024
#define DMA_SIZE 1024
#define EMIF_ADDR 0x02000000 //CE2

char dst[BUF_SIZE];
#pragma DATA_SECTION (dst, ".sysmem")
#pragma DATA_ALIGN (src, 128)

void main( void )
{
int chan = 0; //DMA channel 0
PARAMSET *param = (PARAMSET *) (EDMA_PARAM_BASE + EDMA_PARAM_SIZE * chan);

param->opt = 0x00100109;
param->src = (Uint32) EMIF_ADDR;
param->dst = (Uint32) dst;
param->bcnt = 1;
param->acnt = DMA_SIZE;
param->dstbidx = 0;
param->srcbidx = 0;
param->bcntrld = 0;
param->link = 0xffff;
param->srccidx = 0;
param->dstcidx = 0;
param->ccnt = 1;

....

Regards,

Alexander.

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synchronous EMIF read on DM365