TDA4VM: Ethfw does not run on QNX+ROS

shen jeff

Prodigy 90 points

Part Number: TDA4VM

Hi,

The two SDKS I use are Ti-processor-SDK-qnx_J721E_08_00_00 and Ti-processor-SDK-qnx_J721E_08_00_00.

I have a problem that ethFW is not running.

The LOG is as follows:

Fullscreen TDA4-QNX_RTOS.log Download

U-Boot SPL 2020.01-dirty (Aug 12 2021 - 16:50:42 +0800)
SYSFW ABI: 3.1 (firmware rev 0x0015 '21.1.1--v2021.01a (Terrific Lla')
Trying to boot from MMC2
Loading Environment from MMC... *** Warning - No MMC card found, using default environment

Starting ATF on ARM64 core...

NOTICE:  BL31: v2.4(release):07.03.00.005-dirty
NOTICE:  BL31: Built : 00:15:40, Apr 10 2021

U-Boot SPL 2020.01-dirty (Aug 12 2021 - 16:50:19 +0800)
SYSFW ABI: 3.1 (firmware rev 0x0015 '21.1.1--v2021.01a (Terrific Lla')
Trying to boot from MMC2


U-Boot 2020.01-dirty (Aug 12 2021 - 16:50:19 +0800)

SoC:   J721E SR1.0
Model: Texas Instruments K3 J721E SoC
Board: J721EX-PM2-SOM rev E7
DRAM:  4 GiB
Flash: 0 Bytes
MMC:   sdhci@4f80000: 0, sdhci@4fb0000: 1
Loading Environment from MMC... Card did not respond to voltage select!
mmc_init: -95, time 45
*** Warning - No block device, using default environment

In:    serial@2800000
Out:   serial@2800000
Err:   serial@2800000
Net:   Could not get PHY for ethernet@46000000: addr 0
phy_connect() failed
No ethernet found.

Hit any key to stop autoboot:  2  1  0 
switch to partitions #0, OK
mmc1 is current device
SD/MMC found on device 1
526 bytes read in 3 ms (170.9 KiB/s)
Loaded env from uEnv.txt
Importing environment from mmc1 ...
Running uenvcmd ...
Core 1 is already in use. No rproc commands work
Core 2 is already in use. No rproc commands work
2538652 bytes read in 109 ms (22.2 MiB/s)
Load Remote Processor 2 with data@addr=0x82000000 2538652 bytes: Success!
502680 bytes read in 24 ms (20 MiB/s)
Load Remote Processor 3 with data@addr=0x82000000 502680 bytes: Success!
1579088 bytes read in 66 ms (22.8 MiB/s)
Load Remote Processor 6 with data@addr=0x82000000 1579088 bytes: Success!
1579088 bytes read in 66 ms (22.8 MiB/s)
Load Remote Processor 7 with data@addr=0x82000000 1579088 bytes: Success!
8211068 bytes read in 344 ms (22.8 MiB/s)
## Starting application at 0x80080000 ...
MMU: 16-bit ASID 44-bit PA TCR_EL1=b5183519
cpu0: MPIDR=80000000
cpu0: MIDR=411fd080 Cortex-A72 r1p0
cpu0: CWG=4 ERG=4 Dminline=4 Iminline=4 PIPT
cpu0: CLIDR=a200023 LoUU=1 LoC=2 LoUIS=1
cpu0: L1 Icache 48K linesz=64 set/way=256/3
cpu0: L1 Dcache 32K linesz=64 set/way=256/2
cpu0: L2 Unified 1024K linesz=64 set/way=1024/16
Display set to R5
Loading IFS...decompressing...done
cpu1: MPIDR=80000001
cpu1: MIDR=411fd080 Cortex-A72 r1p0
cpu1: CWG=4 ERG=4 Dminline=4 Iminline=4 PIPT
cpu1: CLIDR=a200023 LoUU=1 LoC=2 LoUIS=1
cpu1: L1 Icache 48K linesz=64 set/way=256/3
cpu1: L1 Dcache 32K linesz=64 set/way=256/2
cpu1: L2 Unified 1024K linesz=64 set/way=1024/16

System page at phys:0000000080011000 user:ffffff8040254000 kern:ffffff8040251000
Starting next program at vffffff80600883c0
All ClockCycles offsets within tolerance
Welcome to QNX Neutrino 7.1.0 on the TI J721E EVM Board!!
Starting random service ...
start serial driver
Starting MMC/SD memory card driver... eMMC
Starting MMC/SD memory card driver... SD
Starting XHCI driver on USB3SS0 and USB3SS1
xpt_configure:  No sdmmc interfaces found
Setting environment variables...
done..
Mounting the sd ..
Looking for user script to run: /ti_fs/scripts/user.sh
Running user script...
user.sh called...
Setting additional environment variables...
Starting tisci-mgr..
Starting shmemallocator..
Starting tiipc-mgr..
Starting TI IPC Resmgr
Starting tiudma-mgr..
Start screen..
screen started with dss_on_r5 configuration..
Initing eMMC ..
Unable to access /dev/emmc0
Mounting /data ..
done...
J7EVM@QNX:/# 

J7EVM@QNX:/# VIA   vis   vision_apps_            vision_apps_init.sh 

J7EVM@QNX:/# [MCU2_0]      3.374585 s: CIO: Init ... Done !!!

[MCU2_0]      3.374636 s: ### CPU Frequency = 1000000000 Hz

[MCU2_0]      3.374665 s: APP: Init ... !!!

[MCU2_0]      3.374682 s: SCICLIENT: Init ... !!!

[MCU2_0]      3.374871 s: SCICLIENT: DMSC FW version [21.1.1--v2021.01a (Terrific Lla]

[MCU2_0]      3.374905 s: SCICLIENT: DMSC FW revision 0x15  

[MCU2_0]      3.374926 s: SCICLIENT: DMSC FW ABI revision 3.1

[MCU2_0]      3.374950 s: SCICLIENT: Init ... Done !!!

[MCU2_0]      3.374969 s: UDMA: Init ... !!!

[MCU2_0]      3.375900 s: UDMA: Init ... Done !!!

[MCU2_0]      3.375947 s: MEM: Init ... !!!

[MCU2_0]      3.375981 s: MEM: Created heap (DDR_SHARED_MEM, id=0, flags=0x00000004) @ e1000000 of size 16777216 bytes !!!

[MCU2_0]      3.376034 s: MEM: Created heap (L3_MEM, id=1, flags=0x00000000) @ 3600000 of size 262144 bytes !!!

[MCU2_0]      3.376078 s: MEM: Created heap (DDR_NON_CACHE_ME, id=5, flags=0x00000000) @ d8000000 of size 16777216 bytes !!!

[MCU2_0]      3.376121 s: MEM: Init ... Done !!!

[MCU2_0]      3.376140 s: IPC: Init ... !!!

[MCU2_0]      3.376181 s: IPC: 6 CPUs participating in IPC !!!

[MCU2_0]      3.380921 s: IPC: Init ... Done !!!

[MCU2_0]      3.380971 s: APP: Syncing with 5 CPUs ... !!!

[MCU2_1]      3.359264 s: CIO: Init ... Done !!!

[MCU2_1]      3.359314 s: ### CPU Frequency = 1000000000 Hz

[MCU2_1]      3.359345 s: APP: Init ... !!!

[MCU2_1]      3.359364 s: SCICLIENT: Init ... !!!

[MCU2_1]      3.359555 s: SCICLIENT: DMSC FW version [21.1.1--v2021.01a (Terrific Lla]

[MCU2_1]      3.359591 s: SCICLIENT: DMSC FW revision 0x15  

[MCU2_1]      3.359614 s: SCICLIENT: DMSC FW ABI revision 3.1

[MCU2_1]      3.359638 s: SCICLIENT: Init ... Done !!!

[MCU2_1]      3.359659 s: UDMA: Init ... !!!

[MCU2_1]      3.360746 s: UDMA: Init ... Done !!!

[MCU2_1]      3.360790 s: MEM: Init ... !!!

[MCU2_1]      3.360820 s: MEM: Created heap (DDR_SHARED_MEM, id=0, flags=0x00000004) @ e2000000 of size 16777216 bytes !!!

[MCU2_1]      3.360871 s: MEM: Created heap (L3_MEM, id=1, flags=0x00000001) @ 3640000 of size 262144 bytes !!!

[MCU2_1]      3.360925 s: MEM: Created heap (DDR_NON_CACHE_ME, id=5, flags=0x00000000) @ d9000000 of size 117440512 bytes !!!

[MCU2_1]      3.360968 s: MEM: Init ... Done !!!

[MCU2_1]      3.360986 s: IPC: Init ... !!!

[MCU2_1]      3.361031 s: IPC: 6 CPUs participating in IPC !!!

[MCU2_1]      3.365823 s: IPC: Init ... Done !!!

[MCU2_1]      3.365870 s: APP: Syncing with 5 CPUs ... !!!

[C6x_1 ]      3.431415 s: CIO: Init ... Done !!!

[C6x_1 ]      3.431439 s: ### CPU Frequency = 1350000000 Hz

[C6x_1 ]      3.431449 s: APP: Init ... !!!

[C6x_1 ]      3.431457 s: SCICLIENT: Init ... !!!

[C6x_1 ]      3.431633 s: SCICLIENT: DMSC FW version [21.1.1--v2021.01a (Terrific Lla]

[C6x_1 ]      3.431647 s: SCICLIENT: DMSC FW revision 0x15  

[C6x_1 ]      3.431657 s: SCICLIENT: DMSC FW ABI revision 3.1

[C6x_1 ]      3.431667 s: SCICLIENT: Init ... Done !!!

[C6x_1 ]      3.431676 s: UDMA: Init ... !!!

[C6x_1 ]      3.432834 s: UDMA: Init ... Done !!!

[C6x_1 ]      3.432856 s: MEM: Init ... !!!

[C6x_1 ]      3.432867 s: MEM: Created heap (DDR_SHARED_MEM, id=0, flags=0x00000004) @ e4000000 of size 16777216 bytes !!!

[C6x_1 ]      3.432885 s: MEM: Created heap (L2_MEM, id=2, flags=0x00000001) @ 800000 of size 229376 bytes !!!

[C6x_1 ]      3.432901 s: MEM: Created heap (DDR_SCRATCH_MEM, id=4, flags=0x00000001) @ e5000000 of size 50331648 bytes !!!

[C6x_1 ]      3.432917 s: MEM: Init ... Done !!!

[C6x_1 ]      3.432925 s: IPC: Init ... !!!

[C6x_1 ]      3.432945 s: IPC: 6 CPUs participating in IPC !!!

[C6x_1 ]      3.436104 s: IPC: Init ... Done !!!

[C6x_1 ]      3.436130 s: APP: Syncing with 5 CPUs ... !!!

[C6x_2 ]      3.513295 s: CIO: Init ... Done !!!

[C6x_2 ]      3.513319 s: ### CPU Frequency = 1350000000 Hz

[C6x_2 ]      3.513329 s: APP: Init ... !!!

[C6x_2 ]      3.513337 s: SCICLIENT: Init ... !!!

[C6x_2 ]      3.513512 s: SCICLIENT: DMSC FW version [21.1.1--v2021.01a (Terrific Lla]

[C6x_2 ]      3.513526 s: SCICLIENT: DMSC FW revision 0x15  

[C6x_2 ]      3.513535 s: SCICLIENT: DMSC FW ABI revision 3.1

[C6x_2 ]      3.513545 s: SCICLIENT: Init ... Done !!!

[C6x_2 ]      3.513554 s: UDMA: Init ... !!!

[C6x_2 ]      3.514715 s: UDMA: Init ... Done !!!

[C6x_2 ]      3.514738 s: MEM: Init ... !!!

[C6x_2 ]      3.514749 s: MEM: Created heap (DDR_SHARED_MEM, id=0, flags=0x00000004) @ e8000000 of size 16777216 bytes !!!

[C6x_2 ]      3.514767 s: MEM: Created heap (L2_MEM, id=2, flags=0x00000001) @ 800000 of size 229376 bytes !!!

[C6x_2 ]      3.514782 s: MEM: Created heap (DDR_SCRATCH_MEM, id=4, flags=0x00000001) @ e9000000 of size 50331648 bytes !!!

[C6x_2 ]      3.514798 s: MEM: Init ... Done !!!

[C6x_2 ]      3.514805 s: IPC: Init ... !!!

[C6x_2 ]      3.514824 s: IPC: 6 CPUs participating in IPC !!!

[C6x_2 ]      3.518005 s: IPC: Init ... Done !!!

[C6x_2 ]      3.518032 s: APP: Syncing with 5 CPUs ... !!!



J7EVM@QNX:/# 

J7EVM@QNX:/# 

J7EVM@QNX:/#

over 3 years ago

0 shen jeff over 3 years ago

Prodigy 90 points

Hi,

I think if normal, there will be a print like this:

MCU2_0] 20.419916s: ETHFW: Init...!!!!!!!!!

[MCU2_0] 20.478311s: CPSW_9G Test on MAIN NAVSS

0 Vineet Roy over 3 years ago in reply to shen jeff

TI__Mastermind 37435 points

Hi,

shen jeff said:
The two SDKS I use are Ti-processor-SDK-qnx_J721E_08_00_00 and Ti-processor-SDK-qnx_J721E_08_00_00.

Did you mean Processor SDK RTOS 8.0.0 ? Are you testing on the EVM or your HW ? Can you share your build and flashing steps ?

Regards

Vineet

0 shen jeff over 3 years ago in reply to Vineet Roy

Prodigy 90 points

Hi Vineet,

1. yes. Processor SDK RTOS 8.0.0

2. our own HW.

3. Build and Flashing Steps are as follows

1) make sdk -j10

2) make qnx_fs_create_sd

3) make qnx_fs_install_sd

BRs

jeff

0 shen jeff over 3 years ago in reply to shen jeff

Prodigy 90 points

Hi Vineet,

After debugging , I found ethfw hang in appLogCpuSyncInit(), I add some prints as below:

360 void appLogCpuSyncInit(uint32_t master_cpu_id, uint32_t self_cpu_id,
361     ┊   uint32_t sync_cpu_id_list[], uint32_t num_cpus)
362 {
363     if(self_cpu_id==master_cpu_id)
364     {
365     ┊   uint32_t i, slave_cpu_id;
366
367     ┊   /* master CPU, sync with each slave CPU */
368     ┊   for(i=0; i<num_cpus; i++)
369     ┊   {
370     ┊   ┊   slave_cpu_id = sync_cpu_id_list[i];
371     ┊   ┊   appLogPrintf("zongmu appLogCpuSyncInit: slave_cpu_id : %d\n", slave_cpu_id);
372     ┊   ┊   //if(slave_cpu_id != self_cpu_id  && slave_cpu_id != APP_IPC_CPU_C7x_1 && master_cpu_id != APP_IPC_CPU_MCU2_0) //zongmu
373     ┊   ┊   if(slave_cpu_id != self_cpu_id)
374     ┊   ┊   {
375     ┊   ┊   ┊   appLogCpuSyncWithSlave(slave_cpu_id);
376     ┊   ┊   }
377     ┊   ┊   appLogPrintf("zongmu appLogCpuSyncInit: slave_cpu_id : %d  done\n", slave_cpu_id);
378     ┊   }
379     ┊   /* all slaves have finished their init, now start all slave's */
380     ┊   for(i=0; i<num_cpus; i++)
381     ┊   {
382     ┊   ┊   slave_cpu_id = sync_cpu_id_list[i];
383     ┊   ┊   appLogPrintf("zongmu appLogCpuSyncInit: slave_cpu_id : %d\n", slave_cpu_id);
384     ┊   ┊   //if(slave_cpu_id != self_cpu_id  && slave_cpu_id != APP_IPC_CPU_C7x_1 && master_cpu_id != APP_IPC_CPU_MCU2_0) //zongmu
385     ┊   ┊   if(slave_cpu_id != self_cpu_id)
386     ┊   ┊   {
387     ┊   ┊   ┊   appLogCpuSyncStartSlave(slave_cpu_id);
388     ┊   ┊   }
389     ┊   ┊   appLogPrintf("zongmu appLogCpuSyncInit: slave_cpu_id : %d  done  2222\n", slave_cpu_id);
390     ┊   }
391     }
392     else
393     {
394     ┊   /* slave CPU, sync's with master CPU */
395     ┊   appLogCpuSyncWithMaster(self_cpu_id);
396     }
397 }

I found that it failed to sync with the cord with cord ID 9(C7X_1), So it's hanging here.

I don't know why c7X_1 core doesn't work on our board,

I changed the code to not sync with Core C7X_1, but QNX didn't start successfully.

change code as below:

60 void appLogCpuSyncInit(uint32_t master_cpu_id, uint32_t self_cpu_id,
361     ┊   uint32_t sync_cpu_id_list[], uint32_t num_cpus)
362 {
363     if(self_cpu_id==master_cpu_id)
364     {
365     ┊   uint32_t i, slave_cpu_id;
366
367     ┊   /* master CPU, sync with each slave CPU */
368     ┊   for(i=0; i<num_cpus; i++)
369     ┊   {
370     ┊   ┊   slave_cpu_id = sync_cpu_id_list[i];
371     ┊   ┊   appLogPrintf("zongmu appLogCpuSyncInit: slave_cpu_id : %d\n", slave_cpu_id);
372     ┊   ┊   if(slave_cpu_id != self_cpu_id  && slave_cpu_id != APP_IPC_CPU_C7x_1 && master_cpu_id != APP_IPC_CPU_MCU2_0) //zongmu
373     ┊   ┊   //if(slave_cpu_id != self_cpu_id)
374     ┊   ┊   {
375     ┊   ┊   ┊   appLogCpuSyncWithSlave(slave_cpu_id);
376     ┊   ┊   }
377     ┊   ┊   appLogPrintf("zongmu appLogCpuSyncInit: slave_cpu_id : %d  done\n", slave_cpu_id);
378     ┊   }
379     ┊   /* all slaves have finished their init, now start all slave's */
380     ┊   for(i=0; i<num_cpus; i++)
381     ┊   {
382     ┊   ┊   slave_cpu_id = sync_cpu_id_list[i];
383     ┊   ┊   appLogPrintf("zongmu appLogCpuSyncInit: slave_cpu_id : %d\n", slave_cpu_id);
384     ┊   ┊   if(slave_cpu_id != self_cpu_id  && slave_cpu_id != APP_IPC_CPU_C7x_1 && master_cpu_id != APP_IPC_CPU_MCU2_0) //zongmu
385     ┊   ┊   //if(slave_cpu_id != self_cpu_id)
386     ┊   ┊   {
387     ┊   ┊   ┊   appLogCpuSyncStartSlave(slave_cpu_id);
388     ┊   ┊   }
389     ┊   ┊   appLogPrintf("zongmu appLogCpuSyncInit: slave_cpu_id : %d  done  2222\n", slave_cpu_id);
390     ┊   }
391     }
392     else
393     {
394     ┊   /* slave CPU, sync's with master CPU */
395     ┊   appLogCpuSyncWithMaster(self_cpu_id);
396     }
397 }

how to change code in order to not sync with c7x_1?

Thanks!

jeff

0 shen jeff over 3 years ago in reply to shen jeff

Prodigy 90 points

Hi Vineet，

Ethfw configured the UART pin to a different mode, resulting in no LOG output actually

BRs

jeff

0 shen jeff over 3 years ago in reply to shen jeff

Prodigy 90 points

Hi Vineet，

Ethfw configured the UART pin to a different mode, resulting in no LOG output actually

BRs

jeff

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TDA4VM: Ethfw does not run on QNX+ROS