Part Number: AM6442
Hi,
I'm trying to bring up the ethernet in my PCB, which includes XAM6442ASFGGAALV processor and 3 DP83869HMRGZT.
The Ethernet part is the same as in the EVM TMDS64GPEVM3.
The only exceptions are:
* I'm using 3 DP83869HMRGZT, while in the EVM 2 of those are used, and 1 DP83867IRRGZ.
* The PHY reset lines are connected to 3 different GPIOS (gpio0_20, gpio0_52, gpio0_84), all reset lines are pulled DOWN with a 2.5K resistor.
I modified the k3-am642-evm.dts device tree in order to add reset-gpio values, so the PHYs will step out of reset mode.
I configured the pads as gpios:
AM64X_IOPAD(0x0154, PIN_OUTPUT | PIN_INPUT, 7)
AM64X_IOPAD(0x0150, PIN_OUTPUT | PIN_INPUT, 7)
AM64X_IOPAD(0x00d4, PIN_OUTPUT | PIN_INPUT, 7)
This following part actually works, and the PHY in address 0 is detected
&cpsw3g_mdio {
reset-gpios = <&main_gpio0 84 GPIO_ACTIVE_LOW>;
reset-delay-us = <2>;
cpsw3g_phy0: ethernet-phy@0 {
reg = <0>;
/*ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;*/
tx-internal-delay-ps = <2000>;
ti,fifo-depth = <DP83869_PHYCR_FIFO_DEPTH_4_B_NIB>;
};
};
I tried to add reset to the other 2 phys on addresses 0xf and 0x3, but had no success.
I tried adding reset/reset-gpios values to the relevant nodes, but this is not working, and after linux boot, the reset line are not '1'.
The only way I found to release the reset was with "gpio-restart" driver
reset1 {
compatible = "gpio-restart";
gpios = <&main_gpio0 52 1>;
active-delay = <1>;
inactive-delay = <1>;
wait-delay = <1>;
};
reset2 {
compatible = "gpio-restart";
gpios = <&main_gpio0 20 1>;
active-delay = <1>;
inactive-delay = <1>;
wait-delay = <1>;
};
This didn't fixed my issue though, I think that this is because the the gpio-restart driver is called after the mdio bus probe.
I tried to to write the gpio value from u-boot using mw command, but was not able to do so.
In order to configure the pads as gpios, I used:
mw 0x000F40D4 0x00050007 mw 0x000F4150 0x00050007 mw 0x000F4154 0x00050007
But I was not able to set the value '1' in the gpio register, I'm not sure what is the right register address.
I found that the base address for gpio0 is 0x000600000, but not found how to set a specific value for a specific gpio, for example gpio0_20..
This messages are displayed during boot:
# dmesg | grep -i mdio [ 0.926311] libphy: Fixed MDIO Bus: probed [ 2.584845] mdio_bus 8000f00.mdio: mii_bus 8000f00.mdio couldn't get reset GPIO [ 2.901295] davinci_mdio 8000f00.mdio: davinci mdio revision 9.7, bus freq 1000000 [ 2.908891] libphy: 8000f00.mdio: probed [ 2.945841] davinci_mdio 8000f00.mdio: phy[0]: device 8000f00.mdio:00, driver unknown
# dmesg | grep -i phy [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x410fd034] [ 0.000000] arch_timer: cp15 timer(s) running at 200.00MHz (phys). [ 0.926311] libphy: Fixed MDIO Bus: probed [ 2.908891] libphy: 8000f00.mdio: probed [ 2.945841] davinci_mdio 8000f00.mdio: phy[0]: device 8000f00.mdio:00, driver unknown
ifconfig/ethtool output:
# ifconfig eth0 up
[ 783.885894] Generic PHY 8000f00.mdio:00: attached PHY driver [Generic PHY] (mii_bus:phy_addr=8000f00.mdio:00, irq=POLL)
[ 783.887444] j721e-pcie f102000.pcie: host bridge /bus@f4000/pcie@f102000 ranges:
[ 783.904371] j721e-pcie f102000.pcie: IO 0x0068001000..0x0068010fff -> 0x0068001000
# [ 783.912588] j721e-pcie f102000.pcie: MEM 0x0068011000..0x006fffffff -> 0x0068011000
[ 783.920856] j721e-pcie f102000.pcie: IB MEM 0x0000000000..0x0fffffffff -> 0x0000000000
[ 783.931153] am65-cpsw-nuss 8000000.ethernet eth0: Link is Down
# ethtool eth0
Settings for eth0:
Supported ports: [ TP MII ]
Supported link modes: 10baseT/Half 10baseT/Full
100baseT/Half 100baseT/Full
1000baseT/Half 1000baseT/Full
Supported pause frame use: Symmetric Receive-only
Supports auto-negotiation: Yes
Supported FEC modes: Not reported
Advertised link modes: 10baseT/Half 10baseT/Full
100baseT/Half 100baseT/Full
1000baseT/Half 1000baseT/Full
Advertised pause frame use: No
Advertised auto-negotiation: Yes
Advertised FEC modes: Not reported
Speed: Unknown!
Duplex: Unknown! (255)
Port: MII
PHYAD: 0
Transceiver: internal
Auto-negotiation: on
Supports Wake-on: d
Wake-on: d
Current message level: 0x000020f7 (8439)
drv probe link ifdown ifup rx_err tx_err hw
Link detected: no
# ifconfig eth1 up
[ 866.814589] am65-cpsw-nuss 8000000.ethernet: phy /mdio-mux-1/mdio@1/ethernet-phy@3 not found on slave 2
ifconfig: SIOCSIFFLAGS: No such device
My questions are:
* How can I add reset to all PHYs from the device tree?
* How can I write GPIO value using by writing to the gpio register from u-boot? how can I find the address?
Attaching full device tree (many reset/reset-gpios entries are experimental, nothing worked)
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/
*/
/dts-v1/;
#include <dt-bindings/phy/phy.h>
#include <dt-bindings/mux/ti-serdes.h>
#include <dt-bindings/leds/common.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/net/ti-dp83867.h>
#include <dt-bindings/net/ti-dp83869.h>
#include "k3-am642.dtsi"
/ {
compatible = "ti,am642-evm", "ti,am642";
model = "Texas Instruments AM642 Board";
chosen {
stdout-path = "serial2:115200n8";
bootargs = "console=ttyS2,115200n8 earlycon=ns16550a,mmio32,0x02800000";
};
aliases {
ethernet2 = &icssg1_emac0;
ethernet3 = &icssg1_emac1;
};
/*
rgmii2-reset {
compatible = "gpio-restart";
gpios = <&main_gpio0 52 1>;
active-delay = <1>;
inactive-delay = <1>;
wait-delay = <1>;
};
rgmii-reset {
compatible = "gpio-restart";
gpios = <&main_gpio0 20 1>;
active-delay = <1>;
inactive-delay = <1>;
wait-delay = <1>;
};
*/
memory@80000000 {
device_type = "memory";
/* 1G RAM */
reg = <0x00000000 0x40000000 0x00000000 0x40000000>;
};
reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
ranges;
secure_ddr: optee@9e800000 {
reg = <0x00 0x9e800000 0x00 0x01800000>; /* for OP-TEE */
alignment = <0x1000>;
no-map;
};
main_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 {
compatible = "shared-dma-pool";
reg = <0x00 0xa0000000 0x00 0x100000>;
no-map;
};
main_r5fss0_core0_memory_region: r5f-memory@a0100000 {
compatible = "shared-dma-pool";
reg = <0x00 0xa0100000 0x00 0xf00000>;
no-map;
};
main_r5fss0_core1_dma_memory_region: r5f-dma-memory@a1000000 {
compatible = "shared-dma-pool";
reg = <0x00 0xa1000000 0x00 0x100000>;
no-map;
};
main_r5fss0_core1_memory_region: r5f-memory@a1100000 {
compatible = "shared-dma-pool";
reg = <0x00 0xa1100000 0x00 0xf00000>;
no-map;
};
main_r5fss1_core0_dma_memory_region: r5f-dma-memory@a2000000 {
compatible = "shared-dma-pool";
reg = <0x00 0xa2000000 0x00 0x100000>;
no-map;
};
main_r5fss1_core0_memory_region: r5f-memory@a2100000 {
compatible = "shared-dma-pool";
reg = <0x00 0xa2100000 0x00 0xf00000>;
no-map;
};
main_r5fss1_core1_dma_memory_region: r5f-dma-memory@a3000000 {
compatible = "shared-dma-pool";
reg = <0x00 0xa3000000 0x00 0x100000>;
no-map;
};
main_r5fss1_core1_memory_region: r5f-memory@a3100000 {
compatible = "shared-dma-pool";
reg = <0x00 0xa3100000 0x00 0xf00000>;
no-map;
};
rtos_ipc_memory_region: ipc-memories@a5000000 {
reg = <0x00 0xa5000000 0x00 0x00800000>;
alignment = <0x1000>;
no-map;
};
};
evm_12v0: fixedregulator-evm12v0 {
/* main DC jack */
compatible = "regulator-fixed";
regulator-name = "evm_12v0";
regulator-min-microvolt = <12000000>;
regulator-max-microvolt = <12000000>;
regulator-always-on;
regulator-boot-on;
};
vsys_5v0: fixedregulator-vsys5v0 {
/* output of LM5140 */
compatible = "regulator-fixed";
regulator-name = "vsys_5v0";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
vin-supply = <&evm_12v0>;
regulator-always-on;
regulator-boot-on;
};
vsys_3v3: fixedregulator-vsys3v3 {
/* output of LM5140 */
compatible = "regulator-fixed";
regulator-name = "vsys_3v3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
vin-supply = <&evm_12v0>;
regulator-always-on;
regulator-boot-on;
};
vdd_mmc1: fixed-regulator-sd {
/* TPS2051BD */
compatible = "regulator-fixed";
regulator-name = "vdd_mmc1";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
enable-active-high;
vin-supply = <&vsys_3v3>;
gpio = <&exp1 6 GPIO_ACTIVE_HIGH>;
};
vddb: fixedregulator-vddb {
compatible = "regulator-fixed";
regulator-name = "vddb_3v3_display";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
vin-supply = <&vsys_3v3>;
regulator-always-on;
regulator-boot-on;
};
leds {
compatible = "gpio-leds";
led-0 {
label = "am64-evm:red:heartbeat";
gpios = <&exp1 16 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "heartbeat";
function = LED_FUNCTION_HEARTBEAT;
default-state = "off";
};
};
mdio_mux: mux-controller {
compatible = "gpio-mux";
#mux-control-cells = <0>;
mux-gpios = <&exp1 12 GPIO_ACTIVE_HIGH>;
};
mdio_mux_1: mdio-mux-1 {
compatible = "mdio-mux-multiplexer";
mux-controls = <&mdio_mux>;
mdio-parent-bus = <&cpsw3g_mdio>;
#address-cells = <1>;
#size-cells = <0>;
reset-gpios = <&main_gpio0 52 GPIO_ACTIVE_LOW>;
reset = <&main_gpio0 52 GPIO_ACTIVE_LOW>;
status = "okay";
mdio@1 {
reg = <0x1>;
#address-cells = <1>;
#size-cells = <0>;
reset-gpios = <&main_gpio0 52 GPIO_ACTIVE_LOW>;
reset = <&main_gpio0 52 GPIO_ACTIVE_LOW>;
status = "okay";
cpsw3g_phy3: ethernet-phy@3 {
reg = <3>;
reset-names = "phy";
reset-gpios = <&main_gpio0 52 GPIO_ACTIVE_LOW>;
reset = <&main_gpio0 52 GPIO_ACTIVE_LOW>;
reset-assert-us = <2>;
reset-deassert-us = <2>;
status = "okay";
};
};
};
transceiver1: can-phy0 {
compatible = "ti,tcan1042";
#phy-cells = <0>;
max-bitrate = <5000000>;
standby-gpios = <&exp1 8 GPIO_ACTIVE_HIGH>;
};
transceiver2: can-phy1 {
compatible = "ti,tcan1042";
#phy-cells = <0>;
max-bitrate = <5000000>;
standby-gpios = <&exp1 9 GPIO_ACTIVE_HIGH>;
};
icssg1_eth: icssg1-eth {
compatible = "ti,am642-icssg-prueth";
pinctrl-names = "default";
pinctrl-0 = <&icssg1_rgmii1_pins_default>;
sram = <&oc_sram>;
ti,prus = <&pru1_0>, <&rtu1_0>, <&tx_pru1_0>, <&pru1_1>, <&rtu1_1>, <&tx_pru1_1>;
firmware-name = "ti-pruss/am65x-sr2-pru0-prueth-fw.elf",
"ti-pruss/am65x-sr2-rtu0-prueth-fw.elf",
"ti-pruss/am65x-sr2-txpru0-prueth-fw.elf",
"ti-pruss/am65x-sr2-pru1-prueth-fw.elf",
"ti-pruss/am65x-sr2-rtu1-prueth-fw.elf",
"ti-pruss/am65x-sr2-txpru1-prueth-fw.elf";
ti,pruss-gp-mux-sel = <2>, /* MII mode */
<2>,
<2>,
<2>, /* MII mode */
<2>,
<2>;
mii-g-rt = <&icssg1_mii_g_rt>;
mii-rt = <&icssg1_mii_rt>;
iep = <&icssg1_iep0>, <&icssg1_iep1>;
interrupt-parent = <&icssg1_intc>;
interrupts = <24 0 2>, <25 1 3>;
interrupt-names = "tx_ts0", "tx_ts1";
dmas = <&main_pktdma 0xc200 0>, /* egress slice 0 */
<&main_pktdma 0xc201 0>, /* egress slice 0 */
<&main_pktdma 0xc202 0>, /* egress slice 0 */
<&main_pktdma 0xc203 0>, /* egress slice 0 */
<&main_pktdma 0xc204 0>, /* egress slice 1 */
<&main_pktdma 0xc205 0>, /* egress slice 1 */
<&main_pktdma 0xc206 0>, /* egress slice 1 */
<&main_pktdma 0xc207 0>, /* egress slice 1 */
<&main_pktdma 0x4200 0>, /* ingress slice 0 */
<&main_pktdma 0x4201 0>, /* ingress slice 1 */
<&main_pktdma 0x4202 0>, /* mgmnt rsp slice 0 */
<&main_pktdma 0x4203 0>; /* mgmnt rsp slice 1 */
dma-names = "tx0-0", "tx0-1", "tx0-2", "tx0-3",
"tx1-0", "tx1-1", "tx1-2", "tx1-3",
"rx0", "rx1",
"rxmgm0", "rxmgm1";
icssg1_emac0: ethernet-mii0 {
phy-handle = <&icssg1_phy1>;
phy-mode = "rgmii-rxid";
syscon-rgmii-delay = <&main_conf 0x4110>;
/* Filled in by bootloader */
local-mac-address = [00 00 00 00 00 00];
};
icssg1_emac1: ethernet-mii1 {
syscon-rgmii-delay = <&main_conf 0x4114>;
/* Filled in by bootloader */
local-mac-address = [00 00 00 00 00 00];
// status = "disabled";
};
};
};
&oc_sram {
main_r5fss0_core0_sram: r5f-sram@40000 {
reg = <0x40000 0x40000>;
};
main_r5fss0_core1_sram: r5f-sram@80000 {
reg = <0x80000 0x40000>;
};
main_r5fss1_core0_sram: r5f-sram@c0000 {
reg = <0xc0000 0x40000>;
};
main_r5fss1_core1_sram: r5f-sram@100000 {
reg = <0x100000 0x40000>;
};
};
&main_r5fss0_core0 {
mboxes = <&mailbox0_cluster2 &mbox_main_r5fss0_core0>;
memory-region = <&main_r5fss0_core0_dma_memory_region>,
<&main_r5fss0_core0_memory_region>;
sram = <&main_r5fss0_core0_sram>;
};
&main_r5fss0_core1 {
mboxes = <&mailbox0_cluster2 &mbox_main_r5fss0_core1>;
memory-region = <&main_r5fss0_core1_dma_memory_region>,
<&main_r5fss0_core1_memory_region>;
sram = <&main_r5fss0_core1_sram>;
};
&main_r5fss1_core0 {
mboxes = <&mailbox0_cluster4 &mbox_main_r5fss1_core0>;
memory-region = <&main_r5fss1_core0_dma_memory_region>,
<&main_r5fss1_core0_memory_region>;
sram = <&main_r5fss1_core0_sram>;
};
&main_r5fss1_core1 {
mboxes = <&mailbox0_cluster4 &mbox_main_r5fss1_core1>;
memory-region = <&main_r5fss1_core1_dma_memory_region>,
<&main_r5fss1_core1_memory_region>;
sram = <&main_r5fss1_core1_sram>;
};
&main_pmx0 {
main_mmc1_pins_default: main-mmc1-pins-default {
pinctrl-single,pins = <
AM64X_IOPAD(0x0294, PIN_INPUT_PULLUP, 0) /* (J19) MMC1_CMD */
AM64X_IOPAD(0x028c, PIN_INPUT_PULLDOWN, 0) /* (L20) MMC1_CLK */
AM64X_IOPAD(0x0288, PIN_INPUT_PULLUP, 0) /* (K21) MMC1_DAT0 */
AM64X_IOPAD(0x0284, PIN_INPUT_PULLUP, 0) /* (L21) MMC1_DAT1 */
AM64X_IOPAD(0x0280, PIN_INPUT_PULLUP, 0) /* (K19) MMC1_DAT2 */
AM64X_IOPAD(0x027c, PIN_INPUT_PULLUP, 0) /* (K18) MMC1_DAT3 */
AM64X_IOPAD(0x029c, PIN_INPUT, 0) /* (C20) MMC1_SDWP */
AM64X_IOPAD(0x0290, PIN_INPUT, 0) /* MMC1_CLKLB */
>;
};
main_uart0_pins_default: main-uart0-pins-default {
pinctrl-single,pins = <
AM64X_IOPAD(0x0238, PIN_INPUT, 0) /* (B16) UART0_CTSn */
AM64X_IOPAD(0x023c, PIN_OUTPUT, 0) /* (A16) UART0_RTSn */
AM64X_IOPAD(0x0230, PIN_INPUT, 0) /* (D15) UART0_RXD */
AM64X_IOPAD(0x0234, PIN_OUTPUT, 0) /* (C16) UART0_TXD */
>;
};
main_spi0_pins_default: main-spi0-pins-default {
pinctrl-single,pins = <
AM64X_IOPAD(0x0210, PIN_INPUT, 0) /* (D13) SPI0_CLK */
AM64X_IOPAD(0x0208, PIN_OUTPUT, 0) /* (D12) SPI0_CS0 */
AM64X_IOPAD(0x0214, PIN_OUTPUT, 0) /* (A13) SPI0_D0 */
AM64X_IOPAD(0x0218, PIN_INPUT, 0) /* (A14) SPI0_D1 */
>;
};
i2c0_pins: i2c0-pins {
pinctrl-single,pins = <
AM64X_IOPAD(0x0260, PIN_INPUT_PULLUP, 0) /* (A18) I2C0_SCL */
AM64X_IOPAD(0x0264, PIN_INPUT_PULLUP, 0) /* (B18) I2C0_SDA */
>;
};
main_i2c1_pins_default: main-i2c1-pins-default {
pinctrl-single,pins = <
AM64X_IOPAD(0x0268, PIN_INPUT_PULLUP, 0) /* (C18) I2C1_SCL */
AM64X_IOPAD(0x026c, PIN_INPUT_PULLUP, 0) /* (B19) I2C1_SDA */
>;
};
mdio1_pins_default: mdio1-pins-default {
pinctrl-single,pins = <
AM64X_IOPAD(0x01fc, PIN_OUTPUT, 4) /* (R2) PRG0_PRU1_GPO19.MDIO0_MDC */
AM64X_IOPAD(0x01f8, PIN_INPUT, 4) /* (P5) PRG0_PRU1_GPO18.MDIO0_MDIO */
>;
};
rgmii1_pins_default: rgmii1-pins-default {
pinctrl-single,pins = <
AM64X_IOPAD(0x01cc, PIN_INPUT, 4) /* (W5) PRG0_PRU1_GPO7.RGMII1_RD0 */
AM64X_IOPAD(0x01d4, PIN_INPUT, 4) /* (Y5) PRG0_PRU1_GPO9.RGMII1_RD1 */
AM64X_IOPAD(0x01d8, PIN_INPUT, 4) /* (V6) PRG0_PRU1_GPO10.RGMII1_RD2 */
AM64X_IOPAD(0x01f4, PIN_INPUT, 4) /* (V5) PRG0_PRU1_GPO17.RGMII1_RD3 */
AM64X_IOPAD(0x0188, PIN_INPUT, 4) /* (AA5) PRG0_PRU0_GPO10.RGMII1_RXC */
AM64X_IOPAD(0x0184, PIN_INPUT, 4) /* (W6) PRG0_PRU0_GPO9.RGMII1_RX_CTL */
AM64X_IOPAD(0x0124, PIN_OUTPUT, 4) /* (V15) PRG1_PRU1_GPO7.RGMII1_TD0 */
AM64X_IOPAD(0x012c, PIN_OUTPUT, 4) /* (V14) PRG1_PRU1_GPO9.RGMII1_TD1 */
AM64X_IOPAD(0x0130, PIN_OUTPUT, 4) /* (W14) PRG1_PRU1_GPO10.RGMII1_TD2 */
AM64X_IOPAD(0x014c, PIN_OUTPUT, 4) /* (AA14) PRG1_PRU1_GPO17.RGMII1_TD3 */
AM64X_IOPAD(0x00e0, PIN_OUTPUT, 4) /* (U14) PRG1_PRU0_GPO10.RGMII1_TXC */
AM64X_IOPAD(0x00dc, PIN_OUTPUT, 4) /* (U15) PRG1_PRU0_GPO9.RGMII1_TX_CTL */
AM64X_IOPAD(0x0154, PIN_OUTPUT | PIN_INPUT, 7) /* (V12) - PHY RESET*/
>;
};
rgmii2_pins_default: rgmii2-pins-default {
pinctrl-single,pins = <
AM64X_IOPAD(0x0108, PIN_INPUT, 4) /* (W11) PRG1_PRU1_GPO0.RGMII2_RD0 */
AM64X_IOPAD(0x010c, PIN_INPUT, 4) /* (V11) PRG1_PRU1_GPO1.RGMII2_RD1 */
AM64X_IOPAD(0x0110, PIN_INPUT, 4) /* (AA12) PRG1_PRU1_GPO2.RGMII2_RD2 */
AM64X_IOPAD(0x0114, PIN_INPUT, 4) /* (Y12) PRG1_PRU1_GPO3.RGMII2_RD3 */
AM64X_IOPAD(0x0120, PIN_INPUT, 4) /* (U11) PRG1_PRU1_GPO6.RGMII2_RXC */
AM64X_IOPAD(0x0118, PIN_INPUT, 4) /* (W12) PRG1_PRU1_GPO4.RGMII2_RX_CTL */
AM64X_IOPAD(0x0134, PIN_OUTPUT, 4) /* (AA10) PRG1_PRU1_GPO11.RGMII2_TD0 */
AM64X_IOPAD(0x0138, PIN_OUTPUT, 4) /* (V10) PRG1_PRU1_GPO12.RGMII2_TD1 */
AM64X_IOPAD(0x013c, PIN_OUTPUT, 4) /* (U10) PRG1_PRU1_GPO13.RGMII2_TD2 */
AM64X_IOPAD(0x0140, PIN_OUTPUT, 4) /* (AA11) PRG1_PRU1_GPO14.RGMII2_TD3 */
AM64X_IOPAD(0x0148, PIN_OUTPUT, 4) /* (Y10) PRG1_PRU1_GPO16.RGMII2_TXC */
AM64X_IOPAD(0x0144, PIN_OUTPUT, 4) /* (Y11) PRG1_PRU1_GPO15.RGMII2_TX_CTL */
AM64X_IOPAD(0x0150, PIN_OUTPUT | PIN_INPUT, 7) /* (Y13) RESET*/
AM64X_IOPAD(0x00d4, PIN_OUTPUT | PIN_INPUT, 7) /* (U13) - RESET*/
>;
};
main_usb0_pins_default: main-usb0-pins-default {
pinctrl-single,pins = <
AM64X_IOPAD(0x02a8, PIN_OUTPUT, 0) /* (E19) USB0_DRVVBUS */
>;
};
ospi0_pins_default: ospi0-pins-default {
pinctrl-single,pins = <
AM64X_IOPAD(0x0000, PIN_OUTPUT, 0) /* (N20) OSPI0_CLK */
AM64X_IOPAD(0x002c, PIN_OUTPUT, 0) /* (L19) OSPI0_CSn0 */
AM64X_IOPAD(0x000c, PIN_INPUT, 0) /* (M19) OSPI0_D0 */
AM64X_IOPAD(0x0010, PIN_INPUT, 0) /* (M18) OSPI0_D1 */
AM64X_IOPAD(0x0014, PIN_INPUT, 0) /* (M20) OSPI0_D2 */
AM64X_IOPAD(0x0018, PIN_INPUT, 0) /* (M21) OSPI0_D3 */
AM64X_IOPAD(0x001c, PIN_INPUT, 0) /* (P21) OSPI0_D4 */
AM64X_IOPAD(0x0020, PIN_INPUT, 0) /* (P20) OSPI0_D5 */
AM64X_IOPAD(0x0024, PIN_INPUT, 0) /* (N18) OSPI0_D6 */
AM64X_IOPAD(0x0028, PIN_INPUT, 0) /* (M17) OSPI0_D7 */
AM64X_IOPAD(0x0008, PIN_INPUT, 0) /* (N19) OSPI0_DQS */
>;
};
main_mcan0_pins_default: main-mcan0-pins-default {
pinctrl-single,pins = <
AM64X_IOPAD(0x0254, PIN_INPUT, 0) /* (B17) MCAN0_RX */
AM64X_IOPAD(0x0250, PIN_OUTPUT, 0) /* (A17) MCAN0_TX */
>;
};
main_mcan1_pins_default: main-mcan1-pins-default {
pinctrl-single,pins = <
AM64X_IOPAD(0x025c, PIN_INPUT, 0) /* (D17) MCAN1_RX */
AM64X_IOPAD(0x0258, PIN_OUTPUT, 0) /* (C17) MCAN1_TX */
>;
};
icssg1_mdio1_pins_default: icssg1-mdio1-pins-default {
pinctrl-single,pins = <
AM64X_IOPAD(0x015c, PIN_OUTPUT, 0) /* (Y6) PRG1_MDIO0_MDC */
AM64X_IOPAD(0x0158, PIN_INPUT, 0) /* (AA6) PRG1_MDIO0_MDIO */
>;
};
icssg1_rgmii1_pins_default: icssg1-rgmii1-pins-default {
pinctrl-single,pins = <
AM64X_IOPAD(0x00b8, PIN_INPUT, 2) /* (Y7) PRG1_PRU0_GPO0.PRG1_RGMII1_RD0 */
AM64X_IOPAD(0x00bc, PIN_INPUT, 2) /* (U8) PRG1_PRU0_GPO1.PRG1_RGMII1_RD1 */
AM64X_IOPAD(0x00c0, PIN_INPUT, 2) /* (W8) PRG1_PRU0_GPO2.PRG1_RGMII1_RD2 */
AM64X_IOPAD(0x00c4, PIN_INPUT, 2) /* (V8) PRG1_PRU0_GPO3.PRG1_RGMII1_RD3 */
AM64X_IOPAD(0x00d0, PIN_INPUT, 2) /* (AA7) PRG1_PRU0_GPO6.PRG1_RGMII1_RXC */
AM64X_IOPAD(0x00c8, PIN_INPUT, 2) /* (Y8) PRG1_PRU0_GPO4.PRG1_RGMII1_RX_CTL */
AM64X_IOPAD(0x00e4, PIN_INPUT, 2) /* (AA8) PRG1_PRU0_GPO11.PRG1_RGMII1_TD0 */
AM64X_IOPAD(0x00e8, PIN_INPUT, 2) /* (U9) PRG1_PRU0_GPO12.PRG1_RGMII1_TD1 */
AM64X_IOPAD(0x00ec, PIN_INPUT, 2) /* (W9) PRG1_PRU0_GPO13.PRG1_RGMII1_TD2 */
AM64X_IOPAD(0x00f0, PIN_INPUT, 2) /* (AA9) PRG1_PRU0_GPO14.PRG1_RGMII1_TD3 */
AM64X_IOPAD(0x00f8, PIN_INPUT, 2) /* (V9) PRG1_PRU0_GPO16.PRG1_RGMII1_TXC */
AM64X_IOPAD(0x00f4, PIN_INPUT, 2) /* (Y9) PRG1_PRU0_GPO15.PRG1_RGMII1_TX_CTL */
/* AM64X_IOPAD(0x00d4, PIN_OUTPUT | PIN_INPUT, 7) /* (U13) - RESET*/
>;
};
main_ecap0_pins_default: main-ecap0-pins-default {
pinctrl-single,pins = <
AM64X_IOPAD(0x0270, PIN_INPUT, 0) /* (D18) ECAP0_IN_APWM_OUT */
>;
};
};
&main_uart0 {
pinctrl-names = "default";
pinctrl-0 = <&main_uart0_pins_default>;
};
/* main_uart1 is reserved for firmware usage */
&main_uart1 {
status = "reserved";
};
&main_uart2 {
status = "disabled";
};
&main_uart3 {
status = "disabled";
};
&main_uart4 {
status = "disabled";
};
&main_uart5 {
status = "disabled";
};
&main_uart6 {
status = "disabled";
};
&mcu_uart0 {
status = "disabled";
};
&mcu_uart1 {
status = "disabled";
};
&main_i2c0 {
pinctrl-names = "default";
pinctrl-0 = <&i2c0_pins>;
clock-frequency = <400000>;
};
&main_i2c1 {
pinctrl-names = "default";
pinctrl-0 = <&main_i2c1_pins_default>;
clock-frequency = <400000>;
exp1: gpio@22 {
compatible = "ti,tca6424";
reg = <0x22>;
gpio-controller;
#gpio-cells = <2>;
gpio-line-names = "GPIO_eMMC_RSTn", "CAN_MUX_SEL",
"GPIO_CPSW1_RST", "GPIO_RGMII1_RST",
"GPIO_RGMII2_RST", "GPIO_PCIe_RST_OUT",
"MMC1_SD_EN", "FSI_FET_SEL",
"MCAN0_STB_3V3", "MCAN1_STB_3V3",
"CPSW_FET_SEL", "CPSW_FET2_SEL",
"PRG1_RGMII2_FET_SEL", "TEST_GPIO2",
"GPIO_OLED_RESETn", "VPP_LDO_EN",
"TEST_LED1", "TP92", "TP90", "TP88",
"TP87", "TP86", "TP89", "TP91";
};
};
&main_i2c2 {
status = "disabled";
};
&main_i2c3 {
status = "disabled";
};
/* mcu_gpio0 is reserved for mcu firmware usage */
&mcu_gpio0 {
status = "reserved";
};
&mcu_i2c0 {
status = "disabled";
};
&mcu_i2c1 {
status = "disabled";
};
&mcu_spi0 {
status = "disabled";
};
&mcu_spi1 {
status = "disabled";
};
&main_spi0 {
pinctrl-names = "default";
pinctrl-0 = <&main_spi0_pins_default>;
ti,pindir-d0-out-d1-in = <1>;
eeprom@0 {
compatible = "microchip,93lc46b";
reg = <0>;
spi-max-frequency = <1000000>;
spi-cs-high;
data-size = <16>;
};
};
&sdhci0 {
/* emmc */
bus-width = <8>;
non-removable;
ti,driver-strength-ohm = <50>;
disable-wp;
no-1-8-v;
};
&sdhci1 {
/* SD/MMC */
pinctrl-names = "default";
bus-width = <4>;
pinctrl-0 = <&main_mmc1_pins_default>;
cd-gpios = <&main_gpio1 77 1>;
ti,driver-strength-ohm = <50>;
disable-wp;
};
&usbss0 {
ti,vbus-divider;
ti,usb2-only;
};
&usb0 {
dr_mode = "otg";
maximum-speed = "high-speed";
pinctrl-names = "default";
pinctrl-0 = <&main_usb0_pins_default>;
};
&cpsw3g {
pinctrl-names = "default";
pinctrl-0 = <&mdio1_pins_default
&rgmii1_pins_default
&rgmii2_pins_default>;
cpts@3d000 {
ti,pps = <7 1>;
};
};
&cpsw_port1 {
phy-mode = "rgmii-rxid";
phy-handle = <&cpsw3g_phy0>;
reset-gpios = <&main_gpio0 52 GPIO_ACTIVE_LOW>;
reset-delay-us = <2>;
};
&cpsw_port2 {
reset-gpios = <&main_gpio0 20 GPIO_ACTIVE_LOW>;
reset-delay-us = <2>;
phy-mode = "rgmii-rxid";
phy-handle = <&cpsw3g_phy3>;
};
&cpsw3g_mdio {
reset-gpios = <&main_gpio0 84 GPIO_ACTIVE_LOW>;
reset-delay-us = <2>;
cpsw3g_phy0: ethernet-phy@0 {
reg = <0>;
/*ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;*/
tx-internal-delay-ps = <2000>;
ti,fifo-depth = <DP83869_PHYCR_FIFO_DEPTH_4_B_NIB>;
// reset-gpios = <&main_gpio0 84 1>;
// reset-delay-us = <2>;
reset = <&main_gpio0 84 GPIO_ACTIVE_LOW>;
};
};
#define TS_OFFSET(pa, val) (0x4+(pa)*4) (0x10000 | val)
×ync_router {
pinctrl-names = "default";
pinctrl-0 = <&mcu_cpts_pps>;
/* Example of the timesync routing */
mcu_cpts_pps: mcu-cpts-pps {
pinctrl-single,pins = <
/* pps [cpts genf1] in22 -> out37 [cpts hw8_push] */
TS_OFFSET(37, 22)
/* pps [cpts genf1] in22 -> out25 [SYNC1_OUT pin] */
TS_OFFSET(25, 22)
>;
};
};
&mailbox0_cluster2 {
mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 {
ti,mbox-rx = <0 0 2>;
ti,mbox-tx = <1 0 2>;
};
mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 {
ti,mbox-rx = <2 0 2>;
ti,mbox-tx = <3 0 2>;
};
};
&mailbox0_cluster3 {
status = "disabled";
};
&mailbox0_cluster4 {
mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 {
ti,mbox-rx = <0 0 2>;
ti,mbox-tx = <1 0 2>;
};
mbox_main_r5fss1_core1: mbox-main-r5fss1-core1 {
ti,mbox-rx = <2 0 2>;
ti,mbox-tx = <3 0 2>;
};
};
&mailbox0_cluster5 {
status = "disabled";
};
&mailbox0_cluster6 {
mbox_m4_0: mbox-m4-0 {
ti,mbox-rx = <0 0 2>;
ti,mbox-tx = <1 0 2>;
};
};
&mailbox0_cluster7 {
status = "disabled";
};
&serdes_ln_ctrl {
idle-states = <AM64_SERDES0_LANE0_PCIE0>;
};
&serdes0 {
serdes0_pcie_link: phy@0 {
reg = <0>;
cdns,num-lanes = <1>;
#phy-cells = <0>;
cdns,phy-type = <PHY_TYPE_PCIE>;
resets = <&serdes_wiz0 1>;
};
};
&pcie0_rc {
reset-gpios = <&exp1 5 GPIO_ACTIVE_HIGH>;
phys = <&serdes0_pcie_link>;
phy-names = "pcie-phy";
num-lanes = <1>;
};
&pcie0_ep {
phys = <&serdes0_pcie_link>;
phy-names = "pcie-phy";
num-lanes = <1>;
status = "disabled";
};
&tscadc0 {
/* ADC is reserved for R5 usage */
status = "reserved";
};
&ospi0 {
pinctrl-names = "default";
pinctrl-0 = <&ospi0_pins_default>;
flash@0{
compatible = "jedec,spi-nor";
reg = <0x0>;
spi-tx-bus-width = <8>;
spi-rx-bus-width = <8>;
spi-max-frequency = <25000000>;
cdns,tshsl-ns = <60>;
cdns,tsd2d-ns = <60>;
cdns,tchsh-ns = <60>;
cdns,tslch-ns = <60>;
cdns,read-delay = <4>;
cdns,phy-mode;
#address-cells = <1>;
#size-cells = <1>;
};
};
&main_mcan0 {
pinctrl-names = "default";
pinctrl-0 = <&main_mcan0_pins_default>;
phys = <&transceiver1>;
};
&main_mcan1 {
pinctrl-names = "default";
pinctrl-0 = <&main_mcan1_pins_default>;
phys = <&transceiver2>;
};
&icssg0_mdio {
status = "disabled";
};
&icssg1_mdio {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&icssg1_mdio1_pins_default>;
icssg1_phy1: ethernet-phy@f {
reg = <0xf>;
reset-names = "phy";
reset = <&main_gpio0 20 GPIO_ACTIVE_LOW>;
reset-gpios = <&main_gpio0 20 GPIO_ACTIVE_LOW>;
reset-assert-us = <2>;
reset-deassert-us = <2>;
};
};
&ecap0 {
/* PWM is available on Pin 1 of header J12 */
pinctrl-names = "default";
pinctrl-0 = <&main_ecap0_pins_default>;
};
Thanks!!
