This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

AM5726: DRA7XX cache not supported

Part Number: AM5726
Other Parts Discussed in Thread: SYSBIOS

Hi,

I'm working with a project I created based off of the GPIO_LedBlink_evmAM572x_c66xTestProject example from the evmAM572x processor SDK. I followed the instructions in the PSDK Linux developer's guide to create an IPC project, then added Big Data buffers to the project as well. That all works great, but when I try to enable caching, I get a compile error stating "Cache is not supported for the specified device (DRA7XX)". 

There's quite a bit of documentation on the DSP's L1 and L2 caches, so it seems like I should be able to enable caching. Is there something I need to reconfigure somehow?

Here's my full compile output:

**** Build of configuration Debug for project GPIO_LedBlink_evmAM572x_c66xTestProject_with_ipc_proj_upd ****

"C:\\ti\\ccs930\\ccs\\utils\\bin\\gmake" -k -j 12 all -O 
 
Building file: "../Dsp1.cfg"
Invoking: XDCtools
"C:/ti/xdctools_3_55_02_22_core/xs" --xdcpath="C:/ti/bios_6_76_03_01/packages;C:/ti/pdk_am57xx_1_0_17/packages;C:/ti/edma3_lld_2_12_05_30E/packages;C:/ti/ipc_3_50_04_08/packages;" xdc.tools.configuro -o configPkg -t ti.targets.elf.C66 -p ti.platforms.evmAM572X:dsp1 -r debug -b "C:/git/temp_checkouts/Klondike-B-Frame-Sitara/Core/bld/AM572x/GPIO_LedBlink_evmAM572x_c66xTestProject_with_ipc_proj_upd/config.bld" -c "C:/ti/ccs930/ccs/tools/compiler/ti-cgt-c6000_8.3.5" "../Dsp1.cfg"
making package.mak (because of package.bld) ...
configuring Dsp1.xe66 from package/cfg/Dsp1_pe66.cfg ...
	 SoC Type is 
	 SoC Type is 
Cache is not supported for the specified device (DRA7XX).
Cache is only supported for the following devices on the C66 target:
	TMS320TI816X
	TMS320DA830
	DM37XX
	TMS320CDRA442
	AWR16XX
	TMS320DA802
	TMS320DA803
	TMS320DA804
	TMS320DA805
	TMS320DA807
	TMS320DA808
	TMS320DA810
	TMS320DA828
	TMS320C6747
	TMS320C6745
	TMS320C6743
	OMAPL137
	OMAPL108
	OMAPL118
	OMAPL138
	TMS320DA840
	TMS320DA850
	TMS320C6742
	TMS320C6746
	TMS320C6748
	Arctic
	TMS320CDRA402
	TMS320CDRA404
	TMS320CDRA414
	TMS320CDRA416
	TMS320CDRA444
	TMS320CDRA446
	TMS320CDM740
	TMS320C6A8168
	TMS320TI811X
	TMS320TI814X
	TMS320DM8148
	TMS320DM8168
	TMS320C6A8149
	IWR16XX
	AWR18XX
	IWR18XX
	IWR68XX
subdir_rules.mk:26: recipe for target 'build-542487615-inproc' failed
js: "C:/ti/bios_6_76_03_01/packages/ti/sysbios/family/c64p/Cache.xs", line 438: Error: Cache unsupported on device!
gmake.exe: *** [package.mak:206: package/cfg/Dsp1_pe66.xdl] Error 1
js: "C:/ti/xdctools_3_55_02_22_core/packages/xdc/tools/Cmdr.xs", line 52: Error: xdc.tools.configuro: configuration failed due to earlier errors (status = 2); 'linker.cmd' deleted.
gmake[1]: *** [build-542487615-inproc] Error 1
gmake: *** [build-542487615] Error 2
subdir_rules.mk:23: recipe for target 'build-542487615' failed
gmake: Target 'all' not remade because of errors.

**** Build Finished ****

Thanks,

Jon

  • Hi Jon,

    Cache can be enabled on DSP.

    However, this particular example doesn't take care of cache coherency between the cores so it doesn't work if cache is enabled.

    This is a limitation in the example SW.

    Regards,

    Stanley

  • Hi Stanley,

    Are there any guides or examples showing how to enable the DSP cache and maintain cache coherency? I'm not sure where to start, since I'm not even sure which part of the build process is causing this error or how I would bypass it.

    Thanks,

    Jon

  • Hi Jon,

    Please double-check the exact Cache module that is being pulled into your cfg file.

    AM57xx/DRA7xx has C66x cores and not C64P cores. The SYS/BIOS cache modules are different between the two.

    You should either be using the generic

     xdc.useModule('ti.sysbios.hal.Cache');

         or the C66 core specific

     xdc.useModule('ti.sysbios.family.c66.Cache');

    Your build is directly pulling in ti.sysbios.family.c64p.Cache and sure enough that module and DRA7xx/AM57xx SoCs are incompatible.

    Please see the SYS/BIOS API documentation for both the modules for details. The MAR settings are all available through the C66 specific module only, while the former just provides the basic API.

    We have been using Cache just fine with the tools you mentioned above in IPC 3.x codebase.

    regards

    Suman

  • Hi Suman,

    I included the c66 Cache in my cfg file and it compiled just fine, although it wasn't working before. I was having an issue with my project file automatically including the c64 cache when I changed my folder structure, so maybe that was affecting my ability to include other cache implementations. I'll create another ticket for that issue if it crops up again.

    The documentation you posted is great, thanks for the link! Do you happen to know if there are any code examples in the SDK? I did a top-level search for Cache_wait in any .c files to see if any existing code was using the API and it didn't look like there were any calls outside of any API functions.

    Thanks,

    Jon

  • Hi Jon,

    I haven't seen a Cache_wait() usage Slight smile. It is just a question of synchronous call vs asynchronous call before you can operate on the buffer that you are invoking the Cache API on.

    You can also look up the BIOS_User_Guide.pdf under the docs folder of the SYS/BIOS installation. Please see the Memory->Cache Configuration and Hardware Abstraction Layer->Cache module for also some usage information. The base explaination are more or less in the API documentation I posted before.

    If you are using CCS for compiling your project, there would be an appropriate. folder 

    C66 Cache settings are done through MAR registers, whose granularity is 16 MB. So, you would have to define your memory map accordingly keeping this in mind (you cannot have a Cached and non-cached regions within the same 16 MB address space).

    You can either do these statically in your config file at build time, or using the Cache API at runtime. Here's an example in a IPC 3.x test file that does some static configuration.

    regards

    Suman